//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// The confidential and proprietary information contained in this file may     
// only be used by a person authorised under and to the extent permitted       
// by a subsisting licensing agreement from ARM Limited.                       
//                                                                             
//            (C) COPYRIGHT 2005-2013 ARM Limited.
//                ALL RIGHTS RESERVED                                          
//                                                                             
// This entire notice must be reproduced on all copies of this file            
// and copies of this file may only be made by a person if such person is      
// permitted to do so under the terms of a subsisting license agreement        
// from ARM Limited.                                                           
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Top-Level Verilog file is auto-generated by AMBA Designer ADr3p4-00rel0-build-0086
//                                                                             
// Stitcher: generic_stitcher_core v3.1, built on Sep 18 2013
//                                                                             
// Filename: tbench.v
// Created : Mon May 27 20:11:45 2024                            
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`timescale 1ns/1ps


//-----------------------------------------------------------------------------
// Module Declaration tbench
//-----------------------------------------------------------------------------

module tbench (

);



//-----------------------------------------------------------------------------
// Parameter Declarations
//-----------------------------------------------------------------------------

parameter chiplink_slv_axi4_tpv_ARUSER_WIDTH = 1;
parameter chiplink_slv_axi4_tpv_AWUSER_WIDTH = 1;
parameter chiplink_slv_axi4_tpv_BUSER_WIDTH = 1;
parameter chiplink_slv_axi4_tpv_DriveOnlyOnEnable = 0;
parameter chiplink_slv_axi4_tpv_PortIsInternal = 0;
parameter chiplink_slv_axi4_tpv_RUSER_WIDTH = 1;
parameter chiplink_slv_axi4_tpv_USE_X = 1;
parameter chiplink_slv_axi4_tpv_WUSER_WIDTH = 1;
parameter chiplink_slv_axi4_tpv_combined_issuing_capability = 16;
parameter chiplink_slv_axi4_tpv_leading_writes = 0;
parameter cpu_mst_axi4_ARUSER_WIDTH = 1;
parameter cpu_mst_axi4_AWUSER_WIDTH = 1;
parameter cpu_mst_axi4_BUSER_WIDTH = 1;
parameter cpu_mst_axi4_DriveOnlyOnEnable = 0;
parameter cpu_mst_axi4_MaxWaits = 5000;
parameter cpu_mst_axi4_PortIsInternal = 0;
parameter cpu_mst_axi4_RUSER_WIDTH = 1;
parameter cpu_mst_axi4_RecMaxWaitOn = 1;
parameter cpu_mst_axi4_RecommendOn = 1;
parameter cpu_mst_axi4_USE_X = 1;
parameter cpu_mst_axi4_WUSER_WIDTH = 1;
parameter cpu_mst_axi4_leading_write_depth = 0;
parameter cpu_mst_axi4_read_acceptance_capability = 16;
parameter cpu_mst_axi4_write_acceptance_capability = 16;
parameter dma_axi4_cpu_m_ARUSER_WIDTH = 1;
parameter dma_axi4_cpu_m_AWUSER_WIDTH = 1;
parameter dma_axi4_cpu_m_BUSER_WIDTH = 1;
parameter dma_axi4_cpu_m_DriveOnlyOnEnable = 0;
parameter dma_axi4_cpu_m_PortIsInternal = 0;
parameter dma_axi4_cpu_m_RUSER_WIDTH = 1;
parameter dma_axi4_cpu_m_USE_X = 1;
parameter dma_axi4_cpu_m_WUSER_WIDTH = 1;
parameter dma_axi4_cpu_m_combined_issuing_capability = 16;
parameter dma_axi4_cpu_m_leading_writes = 0;
parameter dma_axi4_cpu_s_ARUSER_WIDTH = 1;
parameter dma_axi4_cpu_s_AWUSER_WIDTH = 1;
parameter dma_axi4_cpu_s_BUSER_WIDTH = 1;
parameter dma_axi4_cpu_s_DriveOnlyOnEnable = 0;
parameter dma_axi4_cpu_s_MaxWaits = 5000;
parameter dma_axi4_cpu_s_PortIsInternal = 0;
parameter dma_axi4_cpu_s_RUSER_WIDTH = 1;
parameter dma_axi4_cpu_s_RecMaxWaitOn = 1;
parameter dma_axi4_cpu_s_RecommendOn = 1;
parameter dma_axi4_cpu_s_USE_X = 1;
parameter dma_axi4_cpu_s_WUSER_WIDTH = 1;
parameter dma_axi4_cpu_s_leading_write_depth = 0;
parameter dma_axi4_cpu_s_read_acceptance_capability = 16;
parameter dma_axi4_cpu_s_write_acceptance_capability = 16;
parameter psram_slv_axi4_ARUSER_WIDTH = 1;
parameter psram_slv_axi4_AWUSER_WIDTH = 1;
parameter psram_slv_axi4_BUSER_WIDTH = 1;
parameter psram_slv_axi4_DriveOnlyOnEnable = 0;
parameter psram_slv_axi4_PortIsInternal = 0;
parameter psram_slv_axi4_RUSER_WIDTH = 1;
parameter psram_slv_axi4_USE_X = 1;
parameter psram_slv_axi4_WUSER_WIDTH = 1;
parameter psram_slv_axi4_combined_issuing_capability = 16;
parameter psram_slv_axi4_leading_writes = 0;
parameter sdram_slv_axi4_ARUSER_WIDTH = 1;
parameter sdram_slv_axi4_AWUSER_WIDTH = 1;
parameter sdram_slv_axi4_BUSER_WIDTH = 1;
parameter sdram_slv_axi4_DriveOnlyOnEnable = 0;
parameter sdram_slv_axi4_PortIsInternal = 0;
parameter sdram_slv_axi4_RUSER_WIDTH = 1;
parameter sdram_slv_axi4_USE_X = 1;
parameter sdram_slv_axi4_WUSER_WIDTH = 1;
parameter sdram_slv_axi4_combined_issuing_capability = 16;
parameter sdram_slv_axi4_leading_writes = 0;
parameter sram_slv_axi4_ARUSER_WIDTH = 1;
parameter sram_slv_axi4_AWUSER_WIDTH = 1;
parameter sram_slv_axi4_BUSER_WIDTH = 1;
parameter sram_slv_axi4_DriveOnlyOnEnable = 0;
parameter sram_slv_axi4_PortIsInternal = 0;
parameter sram_slv_axi4_RUSER_WIDTH = 1;
parameter sram_slv_axi4_USE_X = 1;
parameter sram_slv_axi4_WUSER_WIDTH = 1;
parameter sram_slv_axi4_combined_issuing_capability = 16;
parameter sram_slv_axi4_leading_writes = 0;
parameter vgalcd_mst_axi4_ARUSER_WIDTH = 1;
parameter vgalcd_mst_axi4_AWUSER_WIDTH = 1;
parameter vgalcd_mst_axi4_BUSER_WIDTH = 1;
parameter vgalcd_mst_axi4_DriveOnlyOnEnable = 0;
parameter vgalcd_mst_axi4_MaxWaits = 5000;
parameter vgalcd_mst_axi4_PortIsInternal = 0;
parameter vgalcd_mst_axi4_RUSER_WIDTH = 1;
parameter vgalcd_mst_axi4_RecMaxWaitOn = 1;
parameter vgalcd_mst_axi4_RecommendOn = 1;
parameter vgalcd_mst_axi4_USE_X = 1;
parameter vgalcd_mst_axi4_WUSER_WIDTH = 1;
parameter vgalcd_mst_axi4_leading_write_depth = 0;
parameter vgalcd_mst_axi4_read_acceptance_capability = 16;
parameter vgalcd_mst_axi4_write_acceptance_capability = 16;



//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------




//-----------------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------------

wire           emit_ack_cfg_event;
wire           emit_ack_cpu_mst_axi4_event;
wire           emit_ack_dma_axi4_cpu_s_event;
wire           emit_ack_vgalcd_mst_axi4_event;
wire           emit_ack_chiplink_slv_axi4_tpv_event;
wire           emit_ack_sdram_slv_axi4_event;
wire           emit_ack_dma_axi4_cpu_m_event;
wire           emit_ack_sram_slv_axi4_event;
wire           emit_ack_psram_slv_axi4_event;
wire   [15:0]  wait_data_cfg_event;
wire   [15:0]  wait_data_cpu_mst_axi4_event;
wire   [15:0]  wait_data_dma_axi4_cpu_s_event;
wire   [15:0]  wait_data_vgalcd_mst_axi4_event;
wire   [15:0]  wait_data_chiplink_slv_axi4_tpv_event;
wire   [15:0]  wait_data_sdram_slv_axi4_event;
wire   [15:0]  wait_data_dma_axi4_cpu_m_event;
wire   [15:0]  wait_data_sram_slv_axi4_event;
wire   [15:0]  wait_data_psram_slv_axi4_event;
wire           wait_req_cfg_event;
wire           wait_req_cpu_mst_axi4_event;
wire           wait_req_dma_axi4_cpu_s_event;
wire           wait_req_vgalcd_mst_axi4_event;
wire           wait_req_chiplink_slv_axi4_tpv_event;
wire           wait_req_sdram_slv_axi4_event;
wire           wait_req_dma_axi4_cpu_m_event;
wire           wait_req_sram_slv_axi4_event;
wire           wait_req_psram_slv_axi4_event;
wire   [31:0]  prdata_archinfo_slv_apb4;
wire           pready_archinfo_slv_apb4;
wire           pslverr_archinfo_slv_apb4;
wire           arready_chiplink_slv_axi4_tpv;
wire           awready_chiplink_slv_axi4_tpv;
wire   [3:0]   bid_chiplink_slv_axi4_tpv;
wire   [1:0]   bresp_chiplink_slv_axi4_tpv;
wire           bvalid_chiplink_slv_axi4_tpv;
wire   [15:0]  emit_data_chiplink_slv_axi4_tpv_event;
wire           emit_req_chiplink_slv_axi4_tpv_event;
wire   [31:0]  prdata_chiplink_slv_axi4_tpv_apb;
wire           pready_chiplink_slv_axi4_tpv_apb;
wire           pslverr_chiplink_slv_axi4_tpv_apb;
wire   [63:0]  rdata_chiplink_slv_axi4_tpv;
wire   [3:0]   rid_chiplink_slv_axi4_tpv;
wire           rlast_chiplink_slv_axi4_tpv;
wire   [1:0]   rresp_chiplink_slv_axi4_tpv;
wire           rvalid_chiplink_slv_axi4_tpv;
wire           wait_ack_chiplink_slv_axi4_tpv_event;
wire           wready_chiplink_slv_axi4_tpv;
wire   [31:0]  prdata_clint_slv_apb4;
wire           pready_clint_slv_apb4;
wire           pslverr_clint_slv_apb4;
wire           clk_aud_12288kclk;
wire           clk_aud_12288kclken;
wire           clk_aud_12288kresetn;
wire           clk_core_200_800mclk_r;
wire           clk_core_200_800mclk;
wire           clk_core_200_800mclken;
wire           clk_core_200_800mresetn;
wire           clk_core_200_800mresetn_r;
wire           clk_peri_100mclk_r;
wire           clk_peri_100mclk;
wire           clk_peri_100mclken;
wire           clk_peri_100mresetn;
wire           clk_peri_100mresetn_r;
wire           clk_peri_25mclk_r;
wire           clk_peri_25mclk;
wire           clk_peri_25mclken;
wire           clk_peri_25mresetn;
wire           clk_peri_25mresetn_r;
wire           clk_tb;
wire   [31:0]  prdata_clk_rst_apb;
wire           pready_clk_rst_apb;
wire           pslverr_clk_rst_apb;
wire           resetn_tb;
wire   [15:0]  emit_data_cfg_event;
wire           emit_req_cfg_event;
wire   [31:0]  paddr_clk_rst_apb;
wire           penable_clk_rst_apb;
wire           pselx_clk_rst_apb;
wire           pselx_cpu_mst_axi4_apb;
wire           pselx_dma_axi4_cpu_s_apb;
wire           pselx_vgalcd_mst_axi4_apb;
wire           pselx_chiplink_slv_axi4_tpv_apb;
wire           pselx_sdram_slv_axi4_apb;
wire           pselx_dma_axi4_cpu_m_apb;
wire           pselx_sram_slv_axi4_apb;
wire           pselx_psram_slv_axi4_apb;
wire   [31:0]  pwdata_clk_rst_apb;
wire           pwrite_clk_rst_apb;
wire           wait_ack_cfg_event;
wire   [31:0]  araddr_cpu_mst_axi4_data;
wire   [1:0]   arburst_cpu_mst_axi4_data;
wire   [3:0]   arcache_cpu_mst_axi4_data;
wire   [2:0]   arid_cpu_mst_axi4_data;
wire   [7:0]   arlen_cpu_mst_axi4_data;
wire           arlock_cpu_mst_axi4_data;
wire   [2:0]   arprot_cpu_mst_axi4_data;
wire   [2:0]   arsize_cpu_mst_axi4_data;
wire           arvalid_cpu_mst_axi4_data;
wire   [31:0]  awaddr_cpu_mst_axi4_data;
wire   [1:0]   awburst_cpu_mst_axi4_data;
wire   [3:0]   awcache_cpu_mst_axi4_data;
wire   [2:0]   awid_cpu_mst_axi4_data;
wire   [7:0]   awlen_cpu_mst_axi4_data;
wire           awlock_cpu_mst_axi4_data;
wire   [2:0]   awprot_cpu_mst_axi4_data;
wire   [2:0]   awsize_cpu_mst_axi4_data;
wire           awvalid_cpu_mst_axi4_data;
wire           bready_cpu_mst_axi4_data;
wire   [15:0]  emit_data_cpu_mst_axi4_event;
wire           emit_req_cpu_mst_axi4_event;
wire   [31:0]  prdata_cpu_mst_axi4_apb;
wire           pready_cpu_mst_axi4_apb;
wire           pslverr_cpu_mst_axi4_apb;
wire           rready_cpu_mst_axi4_data;
wire           wait_ack_cpu_mst_axi4_event;
wire   [31:0]  wdata_cpu_mst_axi4_data;
wire           wlast_cpu_mst_axi4_data;
wire   [3:0]   wstrb_cpu_mst_axi4_data;
wire           wvalid_cpu_mst_axi4_data;
wire   [31:0]  prdata_crc_slv_apb4;
wire           pready_crc_slv_apb4;
wire           pslverr_crc_slv_apb4;
wire           arready_dma_axi4_cpu_m;
wire           awready_dma_axi4_cpu_m;
wire   [3:0]   bid_dma_axi4_cpu_m;
wire   [1:0]   bresp_dma_axi4_cpu_m;
wire           bvalid_dma_axi4_cpu_m;
wire   [15:0]  emit_data_dma_axi4_cpu_m_event;
wire           emit_req_dma_axi4_cpu_m_event;
wire   [31:0]  prdata_dma_axi4_cpu_m_apb;
wire           pready_dma_axi4_cpu_m_apb;
wire           pslverr_dma_axi4_cpu_m_apb;
wire   [31:0]  rdata_dma_axi4_cpu_m;
wire   [3:0]   rid_dma_axi4_cpu_m;
wire           rlast_dma_axi4_cpu_m;
wire   [1:0]   rresp_dma_axi4_cpu_m;
wire           rvalid_dma_axi4_cpu_m;
wire           wait_ack_dma_axi4_cpu_m_event;
wire           wready_dma_axi4_cpu_m;
wire   [31:0]  araddr_dma_axi4_cpu_s_data;
wire   [1:0]   arburst_dma_axi4_cpu_s_data;
wire   [3:0]   arcache_dma_axi4_cpu_s_data;
wire   [3:0]   arid_dma_axi4_cpu_s_data;
wire   [7:0]   arlen_dma_axi4_cpu_s_data;
wire           arlock_dma_axi4_cpu_s_data;
wire   [2:0]   arprot_dma_axi4_cpu_s_data;
wire   [2:0]   arsize_dma_axi4_cpu_s_data;
wire           arvalid_dma_axi4_cpu_s_data;
wire   [31:0]  awaddr_dma_axi4_cpu_s_data;
wire   [1:0]   awburst_dma_axi4_cpu_s_data;
wire   [3:0]   awcache_dma_axi4_cpu_s_data;
wire   [3:0]   awid_dma_axi4_cpu_s_data;
wire   [7:0]   awlen_dma_axi4_cpu_s_data;
wire           awlock_dma_axi4_cpu_s_data;
wire   [2:0]   awprot_dma_axi4_cpu_s_data;
wire   [2:0]   awsize_dma_axi4_cpu_s_data;
wire           awvalid_dma_axi4_cpu_s_data;
wire           bready_dma_axi4_cpu_s_data;
wire   [15:0]  emit_data_dma_axi4_cpu_s_event;
wire           emit_req_dma_axi4_cpu_s_event;
wire   [31:0]  prdata_dma_axi4_cpu_s_apb;
wire           pready_dma_axi4_cpu_s_apb;
wire           pslverr_dma_axi4_cpu_s_apb;
wire           rready_dma_axi4_cpu_s_data;
wire           wait_ack_dma_axi4_cpu_s_event;
wire   [63:0]  wdata_dma_axi4_cpu_s_data;
wire           wlast_dma_axi4_cpu_s_data;
wire   [7:0]   wstrb_dma_axi4_cpu_s_data;
wire           wvalid_dma_axi4_cpu_s_data;
wire   [31:0]  prdata_gpio_slv_apb4;
wire           pready_gpio_slv_apb4;
wire           pslverr_gpio_slv_apb4;
wire   [31:0]  prdata_i2c_slv_apb4;
wire           pready_i2c_slv_apb4;
wire           pslverr_i2c_slv_apb4;
wire   [31:0]  prdata_i2s_slv_apb4;
wire           pready_i2s_slv_apb4;
wire           pslverr_i2s_slv_apb4;
wire   [31:0]  prdata_plic_slv_apb4;
wire           pready_plic_slv_apb4;
wire           pslverr_plic_slv_apb4;
wire   [31:0]  prdata_ps2_slv_apb4;
wire           pready_ps2_slv_apb4;
wire           pslverr_ps2_slv_apb4;
wire   [31:0]  prdata_psram_slv_apb4;
wire           pready_psram_slv_apb4;
wire           pslverr_psram_slv_apb4;
wire           arready_psram_slv_axi4;
wire           awready_psram_slv_axi4;
wire   [3:0]   bid_psram_slv_axi4;
wire   [1:0]   bresp_psram_slv_axi4;
wire           bvalid_psram_slv_axi4;
wire   [15:0]  emit_data_psram_slv_axi4_event;
wire           emit_req_psram_slv_axi4_event;
wire   [31:0]  prdata_psram_slv_axi4_apb;
wire           pready_psram_slv_axi4_apb;
wire           pslverr_psram_slv_axi4_apb;
wire   [63:0]  rdata_psram_slv_axi4;
wire   [3:0]   rid_psram_slv_axi4;
wire           rlast_psram_slv_axi4;
wire   [1:0]   rresp_psram_slv_axi4;
wire           rvalid_psram_slv_axi4;
wire           wait_ack_psram_slv_axi4_event;
wire           wready_psram_slv_axi4;
wire   [31:0]  prdata_pwm0_slv_apb4;
wire           pready_pwm0_slv_apb4;
wire           pslverr_pwm0_slv_apb4;
wire   [31:0]  prdata_pwm1_slv_apb4;
wire           pready_pwm1_slv_apb4;
wire           pslverr_pwm1_slv_apb4;
wire   [31:0]  prdata_pwm2_slv_apb4;
wire           pready_pwm2_slv_apb4;
wire           pslverr_pwm2_slv_apb4;
wire   [31:0]  prdata_qspi_slv_apb4;
wire           pready_qspi_slv_apb4;
wire           pslverr_qspi_slv_apb4;
wire   [31:0]  prdata_rcu_slv_apb4;
wire           pready_rcu_slv_apb4;
wire           pslverr_rcu_slv_apb4;
wire   [31:0]  prdata_rng_slv_apb4;
wire           pready_rng_slv_apb4;
wire           pslverr_rng_slv_apb4;
wire   [31:0]  prdata_rtc_slv_apb4;
wire           pready_rtc_slv_apb4;
wire           pslverr_rtc_slv_apb4;
wire           arready_sdram_slv_axi4;
wire           awready_sdram_slv_axi4;
wire   [3:0]   bid_sdram_slv_axi4;
wire   [1:0]   bresp_sdram_slv_axi4;
wire           bvalid_sdram_slv_axi4;
wire   [15:0]  emit_data_sdram_slv_axi4_event;
wire           emit_req_sdram_slv_axi4_event;
wire   [31:0]  prdata_sdram_slv_axi4_apb;
wire           pready_sdram_slv_axi4_apb;
wire           pslverr_sdram_slv_axi4_apb;
wire   [31:0]  rdata_sdram_slv_axi4;
wire   [3:0]   rid_sdram_slv_axi4;
wire           rlast_sdram_slv_axi4;
wire   [1:0]   rresp_sdram_slv_axi4;
wire           rvalid_sdram_slv_axi4;
wire           wait_ack_sdram_slv_axi4_event;
wire           wready_sdram_slv_axi4;
wire   [31:0]  prdata_spfs_slv_apb4_tpv;
wire           pready_spfs_slv_apb4_tpv;
wire           pslverr_spfs_slv_apb4_tpv;
wire   [31:0]  prdata_spi0_slv_apb4;
wire           pready_spi0_slv_apb4;
wire           pslverr_spi0_slv_apb4;
wire   [31:0]  prdata_spi1_slv_apb4;
wire           pready_spi1_slv_apb4;
wire           pslverr_spi1_slv_apb4;
wire           arready_sram_slv_axi4;
wire           awready_sram_slv_axi4;
wire   [3:0]   bid_sram_slv_axi4;
wire   [1:0]   bresp_sram_slv_axi4;
wire           bvalid_sram_slv_axi4;
wire   [15:0]  emit_data_sram_slv_axi4_event;
wire           emit_req_sram_slv_axi4_event;
wire   [31:0]  prdata_sram_slv_axi4_apb;
wire           pready_sram_slv_axi4_apb;
wire           pslverr_sram_slv_axi4_apb;
wire   [63:0]  rdata_sram_slv_axi4;
wire   [3:0]   rid_sram_slv_axi4;
wire           rlast_sram_slv_axi4;
wire   [1:0]   rresp_sram_slv_axi4;
wire           rvalid_sram_slv_axi4;
wire           wait_ack_sram_slv_axi4_event;
wire           wready_sram_slv_axi4;
wire   [31:0]  prdata_tim0_slv_apb4;
wire           pready_tim0_slv_apb4;
wire           pslverr_tim0_slv_apb4;
wire   [31:0]  prdata_tim1_slv_apb4;
wire           pready_tim1_slv_apb4;
wire           pslverr_tim1_slv_apb4;
wire   [31:0]  prdata_tim2_slv_apb4;
wire           pready_tim2_slv_apb4;
wire           pslverr_tim2_slv_apb4;
wire   [31:0]  prdata_tim3_slv_apb4;
wire           pready_tim3_slv_apb4;
wire           pslverr_tim3_slv_apb4;
wire   [31:0]  araddr_chiplink_slv_axi4_tpv;
wire   [31:0]  araddr_dma_axi4_cpu_m;
wire   [31:0]  araddr_psram_slv_axi4;
wire   [31:0]  araddr_sdram_slv_axi4;
wire   [31:0]  araddr_sram_slv_axi4;
wire   [1:0]   arburst_chiplink_slv_axi4_tpv;
wire   [1:0]   arburst_dma_axi4_cpu_m;
wire   [1:0]   arburst_psram_slv_axi4;
wire   [1:0]   arburst_sdram_slv_axi4;
wire   [1:0]   arburst_sram_slv_axi4;
wire   [3:0]   arcache_chiplink_slv_axi4_tpv;
wire   [3:0]   arcache_dma_axi4_cpu_m;
wire   [3:0]   arcache_psram_slv_axi4;
wire   [3:0]   arcache_sdram_slv_axi4;
wire   [3:0]   arcache_sram_slv_axi4;
wire   [3:0]   arid_chiplink_slv_axi4_tpv;
wire   [3:0]   arid_dma_axi4_cpu_m;
wire   [3:0]   arid_psram_slv_axi4;
wire   [3:0]   arid_sdram_slv_axi4;
wire   [3:0]   arid_sram_slv_axi4;
wire   [7:0]   arlen_chiplink_slv_axi4_tpv;
wire   [7:0]   arlen_dma_axi4_cpu_m;
wire   [7:0]   arlen_psram_slv_axi4;
wire   [7:0]   arlen_sdram_slv_axi4;
wire   [7:0]   arlen_sram_slv_axi4;
wire           arlock_chiplink_slv_axi4_tpv;
wire           arlock_dma_axi4_cpu_m;
wire           arlock_psram_slv_axi4;
wire           arlock_sdram_slv_axi4;
wire           arlock_sram_slv_axi4;
wire   [2:0]   arprot_chiplink_slv_axi4_tpv;
wire   [2:0]   arprot_dma_axi4_cpu_m;
wire   [2:0]   arprot_psram_slv_axi4;
wire   [2:0]   arprot_sdram_slv_axi4;
wire   [2:0]   arprot_sram_slv_axi4;
wire           arready_cpu_mst_axi4_data;
wire           arready_dma_axi4_cpu_s_data;
wire           arready_vgalcd_mst_axi4_data;
wire   [2:0]   arsize_chiplink_slv_axi4_tpv;
wire   [2:0]   arsize_dma_axi4_cpu_m;
wire   [2:0]   arsize_psram_slv_axi4;
wire   [2:0]   arsize_sdram_slv_axi4;
wire   [2:0]   arsize_sram_slv_axi4;
wire           arvalid_chiplink_slv_axi4_tpv;
wire           arvalid_dma_axi4_cpu_m;
wire           arvalid_psram_slv_axi4;
wire           arvalid_sdram_slv_axi4;
wire           arvalid_sram_slv_axi4;
wire   [31:0]  awaddr_chiplink_slv_axi4_tpv;
wire   [31:0]  awaddr_dma_axi4_cpu_m;
wire   [31:0]  awaddr_psram_slv_axi4;
wire   [31:0]  awaddr_sdram_slv_axi4;
wire   [31:0]  awaddr_sram_slv_axi4;
wire   [1:0]   awburst_chiplink_slv_axi4_tpv;
wire   [1:0]   awburst_dma_axi4_cpu_m;
wire   [1:0]   awburst_psram_slv_axi4;
wire   [1:0]   awburst_sdram_slv_axi4;
wire   [1:0]   awburst_sram_slv_axi4;
wire   [3:0]   awcache_chiplink_slv_axi4_tpv;
wire   [3:0]   awcache_dma_axi4_cpu_m;
wire   [3:0]   awcache_psram_slv_axi4;
wire   [3:0]   awcache_sdram_slv_axi4;
wire   [3:0]   awcache_sram_slv_axi4;
wire   [3:0]   awid_chiplink_slv_axi4_tpv;
wire   [3:0]   awid_dma_axi4_cpu_m;
wire   [3:0]   awid_psram_slv_axi4;
wire   [3:0]   awid_sdram_slv_axi4;
wire   [3:0]   awid_sram_slv_axi4;
wire   [7:0]   awlen_chiplink_slv_axi4_tpv;
wire   [7:0]   awlen_dma_axi4_cpu_m;
wire   [7:0]   awlen_psram_slv_axi4;
wire   [7:0]   awlen_sdram_slv_axi4;
wire   [7:0]   awlen_sram_slv_axi4;
wire           awlock_chiplink_slv_axi4_tpv;
wire           awlock_dma_axi4_cpu_m;
wire           awlock_psram_slv_axi4;
wire           awlock_sdram_slv_axi4;
wire           awlock_sram_slv_axi4;
wire   [2:0]   awprot_chiplink_slv_axi4_tpv;
wire   [2:0]   awprot_dma_axi4_cpu_m;
wire   [2:0]   awprot_psram_slv_axi4;
wire   [2:0]   awprot_sdram_slv_axi4;
wire   [2:0]   awprot_sram_slv_axi4;
wire           awready_cpu_mst_axi4_data;
wire           awready_dma_axi4_cpu_s_data;
wire           awready_vgalcd_mst_axi4_data;
wire   [2:0]   awsize_chiplink_slv_axi4_tpv;
wire   [2:0]   awsize_dma_axi4_cpu_m;
wire   [2:0]   awsize_psram_slv_axi4;
wire   [2:0]   awsize_sdram_slv_axi4;
wire   [2:0]   awsize_sram_slv_axi4;
wire           awvalid_chiplink_slv_axi4_tpv;
wire           awvalid_dma_axi4_cpu_m;
wire           awvalid_psram_slv_axi4;
wire           awvalid_sdram_slv_axi4;
wire           awvalid_sram_slv_axi4;
wire   [2:0]   bid_cpu_mst_axi4_data;
wire   [3:0]   bid_dma_axi4_cpu_s_data;
wire   [2:0]   bid_vgalcd_mst_axi4_data;
wire           bready_chiplink_slv_axi4_tpv;
wire           bready_dma_axi4_cpu_m;
wire           bready_psram_slv_axi4;
wire           bready_sdram_slv_axi4;
wire           bready_sram_slv_axi4;
wire   [1:0]   bresp_cpu_mst_axi4_data;
wire   [1:0]   bresp_dma_axi4_cpu_s_data;
wire   [1:0]   bresp_vgalcd_mst_axi4_data;
wire           bvalid_cpu_mst_axi4_data;
wire           bvalid_dma_axi4_cpu_s_data;
wire           bvalid_vgalcd_mst_axi4_data;
wire   [31:0]  paddr_archinfo_slv_apb4;
wire   [31:0]  paddr_clint_slv_apb4;
wire   [31:0]  paddr_crc_slv_apb4;
wire   [31:0]  paddr_gpio_slv_apb4;
wire   [31:0]  paddr_i2c_slv_apb4;
wire   [31:0]  paddr_i2s_slv_apb4;
wire   [31:0]  paddr_plic_slv_apb4;
wire   [31:0]  paddr_ps2_slv_apb4;
wire   [31:0]  paddr_psram_slv_apb4;
wire   [31:0]  paddr_pwm0_slv_apb4;
wire   [31:0]  paddr_pwm1_slv_apb4;
wire   [31:0]  paddr_pwm2_slv_apb4;
wire   [31:0]  paddr_qspi_slv_apb4;
wire   [31:0]  paddr_rcu_slv_apb4;
wire   [31:0]  paddr_rng_slv_apb4;
wire   [31:0]  paddr_rtc_slv_apb4;
wire   [31:0]  paddr_spfs_slv_apb4_tpv;
wire   [31:0]  paddr_spi0_slv_apb4;
wire   [31:0]  paddr_spi1_slv_apb4;
wire   [31:0]  paddr_tim0_slv_apb4;
wire   [31:0]  paddr_tim1_slv_apb4;
wire   [31:0]  paddr_tim2_slv_apb4;
wire   [31:0]  paddr_tim3_slv_apb4;
wire   [31:0]  paddr_uart_slv_apb4;
wire   [31:0]  paddr_uart_slv_apb4_tpv;
wire   [31:0]  paddr_vgalcd_slv_apb4;
wire   [31:0]  paddr_wdg_slv_apb4;
wire           penable_archinfo_slv_apb4;
wire           penable_clint_slv_apb4;
wire           penable_crc_slv_apb4;
wire           penable_gpio_slv_apb4;
wire           penable_i2c_slv_apb4;
wire           penable_i2s_slv_apb4;
wire           penable_plic_slv_apb4;
wire           penable_ps2_slv_apb4;
wire           penable_psram_slv_apb4;
wire           penable_pwm0_slv_apb4;
wire           penable_pwm1_slv_apb4;
wire           penable_pwm2_slv_apb4;
wire           penable_qspi_slv_apb4;
wire           penable_rcu_slv_apb4;
wire           penable_rng_slv_apb4;
wire           penable_rtc_slv_apb4;
wire           penable_spfs_slv_apb4_tpv;
wire           penable_spi0_slv_apb4;
wire           penable_spi1_slv_apb4;
wire           penable_tim0_slv_apb4;
wire           penable_tim1_slv_apb4;
wire           penable_tim2_slv_apb4;
wire           penable_tim3_slv_apb4;
wire           penable_uart_slv_apb4;
wire           penable_uart_slv_apb4_tpv;
wire           penable_vgalcd_slv_apb4;
wire           penable_wdg_slv_apb4;
wire   [2:0]   pprot_archinfo_slv_apb4;
wire   [2:0]   pprot_clint_slv_apb4;
wire   [2:0]   pprot_crc_slv_apb4;
wire   [2:0]   pprot_gpio_slv_apb4;
wire   [2:0]   pprot_i2c_slv_apb4;
wire   [2:0]   pprot_i2s_slv_apb4;
wire   [2:0]   pprot_plic_slv_apb4;
wire   [2:0]   pprot_ps2_slv_apb4;
wire   [2:0]   pprot_psram_slv_apb4;
wire   [2:0]   pprot_pwm0_slv_apb4;
wire   [2:0]   pprot_pwm1_slv_apb4;
wire   [2:0]   pprot_pwm2_slv_apb4;
wire   [2:0]   pprot_qspi_slv_apb4;
wire   [2:0]   pprot_rcu_slv_apb4;
wire   [2:0]   pprot_rng_slv_apb4;
wire   [2:0]   pprot_rtc_slv_apb4;
wire   [2:0]   pprot_spfs_slv_apb4_tpv;
wire   [2:0]   pprot_spi0_slv_apb4;
wire   [2:0]   pprot_spi1_slv_apb4;
wire   [2:0]   pprot_tim0_slv_apb4;
wire   [2:0]   pprot_tim1_slv_apb4;
wire   [2:0]   pprot_tim2_slv_apb4;
wire   [2:0]   pprot_tim3_slv_apb4;
wire   [2:0]   pprot_uart_slv_apb4;
wire   [2:0]   pprot_uart_slv_apb4_tpv;
wire   [2:0]   pprot_vgalcd_slv_apb4;
wire   [2:0]   pprot_wdg_slv_apb4;
wire           pselx_archinfo_slv_apb4;
wire           pselx_clint_slv_apb4;
wire           pselx_crc_slv_apb4;
wire           pselx_gpio_slv_apb4;
wire           pselx_i2c_slv_apb4;
wire           pselx_i2s_slv_apb4;
wire           pselx_plic_slv_apb4;
wire           pselx_ps2_slv_apb4;
wire           pselx_psram_slv_apb4;
wire           pselx_pwm0_slv_apb4;
wire           pselx_pwm1_slv_apb4;
wire           pselx_pwm2_slv_apb4;
wire           pselx_qspi_slv_apb4;
wire           pselx_rcu_slv_apb4;
wire           pselx_rng_slv_apb4;
wire           pselx_rtc_slv_apb4;
wire           pselx_spfs_slv_apb4_tpv;
wire           pselx_spi0_slv_apb4;
wire           pselx_spi1_slv_apb4;
wire           pselx_tim0_slv_apb4;
wire           pselx_tim1_slv_apb4;
wire           pselx_tim2_slv_apb4;
wire           pselx_tim3_slv_apb4;
wire           pselx_uart_slv_apb4;
wire           pselx_uart_slv_apb4_tpv;
wire           pselx_vgalcd_slv_apb4;
wire           pselx_wdg_slv_apb4;
wire   [3:0]   pstrb_archinfo_slv_apb4;
wire   [3:0]   pstrb_clint_slv_apb4;
wire   [3:0]   pstrb_crc_slv_apb4;
wire   [3:0]   pstrb_gpio_slv_apb4;
wire   [3:0]   pstrb_i2c_slv_apb4;
wire   [3:0]   pstrb_i2s_slv_apb4;
wire   [3:0]   pstrb_plic_slv_apb4;
wire   [3:0]   pstrb_ps2_slv_apb4;
wire   [3:0]   pstrb_psram_slv_apb4;
wire   [3:0]   pstrb_pwm0_slv_apb4;
wire   [3:0]   pstrb_pwm1_slv_apb4;
wire   [3:0]   pstrb_pwm2_slv_apb4;
wire   [3:0]   pstrb_qspi_slv_apb4;
wire   [3:0]   pstrb_rcu_slv_apb4;
wire   [3:0]   pstrb_rng_slv_apb4;
wire   [3:0]   pstrb_rtc_slv_apb4;
wire   [3:0]   pstrb_spfs_slv_apb4_tpv;
wire   [3:0]   pstrb_spi0_slv_apb4;
wire   [3:0]   pstrb_spi1_slv_apb4;
wire   [3:0]   pstrb_tim0_slv_apb4;
wire   [3:0]   pstrb_tim1_slv_apb4;
wire   [3:0]   pstrb_tim2_slv_apb4;
wire   [3:0]   pstrb_tim3_slv_apb4;
wire   [3:0]   pstrb_uart_slv_apb4;
wire   [3:0]   pstrb_uart_slv_apb4_tpv;
wire   [3:0]   pstrb_vgalcd_slv_apb4;
wire   [3:0]   pstrb_wdg_slv_apb4;
wire   [31:0]  pwdata_archinfo_slv_apb4;
wire   [31:0]  pwdata_clint_slv_apb4;
wire   [31:0]  pwdata_crc_slv_apb4;
wire   [31:0]  pwdata_gpio_slv_apb4;
wire   [31:0]  pwdata_i2c_slv_apb4;
wire   [31:0]  pwdata_i2s_slv_apb4;
wire   [31:0]  pwdata_plic_slv_apb4;
wire   [31:0]  pwdata_ps2_slv_apb4;
wire   [31:0]  pwdata_psram_slv_apb4;
wire   [31:0]  pwdata_pwm0_slv_apb4;
wire   [31:0]  pwdata_pwm1_slv_apb4;
wire   [31:0]  pwdata_pwm2_slv_apb4;
wire   [31:0]  pwdata_qspi_slv_apb4;
wire   [31:0]  pwdata_rcu_slv_apb4;
wire   [31:0]  pwdata_rng_slv_apb4;
wire   [31:0]  pwdata_rtc_slv_apb4;
wire   [31:0]  pwdata_spfs_slv_apb4_tpv;
wire   [31:0]  pwdata_spi0_slv_apb4;
wire   [31:0]  pwdata_spi1_slv_apb4;
wire   [31:0]  pwdata_tim0_slv_apb4;
wire   [31:0]  pwdata_tim1_slv_apb4;
wire   [31:0]  pwdata_tim2_slv_apb4;
wire   [31:0]  pwdata_tim3_slv_apb4;
wire   [31:0]  pwdata_uart_slv_apb4;
wire   [31:0]  pwdata_uart_slv_apb4_tpv;
wire   [31:0]  pwdata_vgalcd_slv_apb4;
wire   [31:0]  pwdata_wdg_slv_apb4;
wire           pwrite_archinfo_slv_apb4;
wire           pwrite_clint_slv_apb4;
wire           pwrite_crc_slv_apb4;
wire           pwrite_gpio_slv_apb4;
wire           pwrite_i2c_slv_apb4;
wire           pwrite_i2s_slv_apb4;
wire           pwrite_plic_slv_apb4;
wire           pwrite_ps2_slv_apb4;
wire           pwrite_psram_slv_apb4;
wire           pwrite_pwm0_slv_apb4;
wire           pwrite_pwm1_slv_apb4;
wire           pwrite_pwm2_slv_apb4;
wire           pwrite_qspi_slv_apb4;
wire           pwrite_rcu_slv_apb4;
wire           pwrite_rng_slv_apb4;
wire           pwrite_rtc_slv_apb4;
wire           pwrite_spfs_slv_apb4_tpv;
wire           pwrite_spi0_slv_apb4;
wire           pwrite_spi1_slv_apb4;
wire           pwrite_tim0_slv_apb4;
wire           pwrite_tim1_slv_apb4;
wire           pwrite_tim2_slv_apb4;
wire           pwrite_tim3_slv_apb4;
wire           pwrite_uart_slv_apb4;
wire           pwrite_uart_slv_apb4_tpv;
wire           pwrite_vgalcd_slv_apb4;
wire           pwrite_wdg_slv_apb4;
wire   [31:0]  rdata_cpu_mst_axi4_data;
wire   [63:0]  rdata_dma_axi4_cpu_s_data;
wire   [63:0]  rdata_vgalcd_mst_axi4_data;
wire   [2:0]   rid_cpu_mst_axi4_data;
wire   [3:0]   rid_dma_axi4_cpu_s_data;
wire   [2:0]   rid_vgalcd_mst_axi4_data;
wire           rlast_cpu_mst_axi4_data;
wire           rlast_dma_axi4_cpu_s_data;
wire           rlast_vgalcd_mst_axi4_data;
wire           rready_chiplink_slv_axi4_tpv;
wire           rready_dma_axi4_cpu_m;
wire           rready_psram_slv_axi4;
wire           rready_sdram_slv_axi4;
wire           rready_sram_slv_axi4;
wire   [1:0]   rresp_cpu_mst_axi4_data;
wire   [1:0]   rresp_dma_axi4_cpu_s_data;
wire   [1:0]   rresp_vgalcd_mst_axi4_data;
wire           rvalid_cpu_mst_axi4_data;
wire           rvalid_dma_axi4_cpu_s_data;
wire           rvalid_vgalcd_mst_axi4_data;
wire   [63:0]  wdata_chiplink_slv_axi4_tpv;
wire   [31:0]  wdata_dma_axi4_cpu_m;
wire   [63:0]  wdata_psram_slv_axi4;
wire   [31:0]  wdata_sdram_slv_axi4;
wire   [63:0]  wdata_sram_slv_axi4;
wire           wlast_chiplink_slv_axi4_tpv;
wire           wlast_dma_axi4_cpu_m;
wire           wlast_psram_slv_axi4;
wire           wlast_sdram_slv_axi4;
wire           wlast_sram_slv_axi4;
wire           wready_cpu_mst_axi4_data;
wire           wready_dma_axi4_cpu_s_data;
wire           wready_vgalcd_mst_axi4_data;
wire   [7:0]   wstrb_chiplink_slv_axi4_tpv;
wire   [3:0]   wstrb_dma_axi4_cpu_m;
wire   [7:0]   wstrb_psram_slv_axi4;
wire   [3:0]   wstrb_sdram_slv_axi4;
wire   [7:0]   wstrb_sram_slv_axi4;
wire           wvalid_chiplink_slv_axi4_tpv;
wire           wvalid_dma_axi4_cpu_m;
wire           wvalid_psram_slv_axi4;
wire           wvalid_sdram_slv_axi4;
wire           wvalid_sram_slv_axi4;
wire   [31:0]  prdata_uart_slv_apb4;
wire           pready_uart_slv_apb4;
wire           pslverr_uart_slv_apb4;
wire   [31:0]  prdata_uart_slv_apb4_tpv;
wire           pready_uart_slv_apb4_tpv;
wire           pslverr_uart_slv_apb4_tpv;
wire   [31:0]  araddr_vgalcd_mst_axi4_data;
wire   [1:0]   arburst_vgalcd_mst_axi4_data;
wire   [3:0]   arcache_vgalcd_mst_axi4_data;
wire   [2:0]   arid_vgalcd_mst_axi4_data;
wire   [7:0]   arlen_vgalcd_mst_axi4_data;
wire           arlock_vgalcd_mst_axi4_data;
wire   [2:0]   arprot_vgalcd_mst_axi4_data;
wire   [2:0]   arsize_vgalcd_mst_axi4_data;
wire           arvalid_vgalcd_mst_axi4_data;
wire   [31:0]  awaddr_vgalcd_mst_axi4_data;
wire   [1:0]   awburst_vgalcd_mst_axi4_data;
wire   [3:0]   awcache_vgalcd_mst_axi4_data;
wire   [2:0]   awid_vgalcd_mst_axi4_data;
wire   [7:0]   awlen_vgalcd_mst_axi4_data;
wire           awlock_vgalcd_mst_axi4_data;
wire   [2:0]   awprot_vgalcd_mst_axi4_data;
wire   [2:0]   awsize_vgalcd_mst_axi4_data;
wire           awvalid_vgalcd_mst_axi4_data;
wire           bready_vgalcd_mst_axi4_data;
wire   [15:0]  emit_data_vgalcd_mst_axi4_event;
wire           emit_req_vgalcd_mst_axi4_event;
wire   [31:0]  prdata_vgalcd_mst_axi4_apb;
wire           pready_vgalcd_mst_axi4_apb;
wire           pslverr_vgalcd_mst_axi4_apb;
wire           rready_vgalcd_mst_axi4_data;
wire           wait_ack_vgalcd_mst_axi4_event;
wire   [63:0]  wdata_vgalcd_mst_axi4_data;
wire           wlast_vgalcd_mst_axi4_data;
wire   [7:0]   wstrb_vgalcd_mst_axi4_data;
wire           wvalid_vgalcd_mst_axi4_data;
wire   [31:0]  prdata_vgalcd_slv_apb4;
wire           pready_vgalcd_slv_apb4;
wire           pslverr_vgalcd_slv_apb4;
wire   [31:0]  prdata_wdg_slv_apb4;
wire           pready_wdg_slv_apb4;
wire           pslverr_wdg_slv_apb4;



//-----------------------------------------------------------------------------
// Sub-Modules Instantiation
//-----------------------------------------------------------------------------

FrmEventDistributor     FrmEvent (
  .wait_req_1           (wait_req_cfg_event),
  .wait_ack_1           (wait_ack_cfg_event),
  .wait_data_1          (wait_data_cfg_event),
  .emit_req_1           (emit_req_cfg_event),
  .emit_ack_1           (emit_ack_cfg_event),
  .emit_data_1          (emit_data_cfg_event),
  .wait_req_2           (wait_req_cpu_mst_axi4_event),
  .wait_ack_2           (wait_ack_cpu_mst_axi4_event),
  .wait_data_2          (wait_data_cpu_mst_axi4_event),
  .emit_req_2           (emit_req_cpu_mst_axi4_event),
  .emit_ack_2           (emit_ack_cpu_mst_axi4_event),
  .emit_data_2          (emit_data_cpu_mst_axi4_event),
  .wait_req_3           (wait_req_dma_axi4_cpu_s_event),
  .wait_ack_3           (wait_ack_dma_axi4_cpu_s_event),
  .wait_data_3          (wait_data_dma_axi4_cpu_s_event),
  .emit_req_3           (emit_req_dma_axi4_cpu_s_event),
  .emit_ack_3           (emit_ack_dma_axi4_cpu_s_event),
  .emit_data_3          (emit_data_dma_axi4_cpu_s_event),
  .wait_req_4           (wait_req_vgalcd_mst_axi4_event),
  .wait_ack_4           (wait_ack_vgalcd_mst_axi4_event),
  .wait_data_4          (wait_data_vgalcd_mst_axi4_event),
  .emit_req_4           (emit_req_vgalcd_mst_axi4_event),
  .emit_ack_4           (emit_ack_vgalcd_mst_axi4_event),
  .emit_data_4          (emit_data_vgalcd_mst_axi4_event),
  .wait_req_5           (wait_req_chiplink_slv_axi4_tpv_event),
  .wait_ack_5           (wait_ack_chiplink_slv_axi4_tpv_event),
  .wait_data_5          (wait_data_chiplink_slv_axi4_tpv_event),
  .emit_req_5           (emit_req_chiplink_slv_axi4_tpv_event),
  .emit_ack_5           (emit_ack_chiplink_slv_axi4_tpv_event),
  .emit_data_5          (emit_data_chiplink_slv_axi4_tpv_event),
  .wait_req_6           (wait_req_sdram_slv_axi4_event),
  .wait_ack_6           (wait_ack_sdram_slv_axi4_event),
  .wait_data_6          (wait_data_sdram_slv_axi4_event),
  .emit_req_6           (emit_req_sdram_slv_axi4_event),
  .emit_ack_6           (emit_ack_sdram_slv_axi4_event),
  .emit_data_6          (emit_data_sdram_slv_axi4_event),
  .wait_req_7           (wait_req_dma_axi4_cpu_m_event),
  .wait_ack_7           (wait_ack_dma_axi4_cpu_m_event),
  .wait_data_7          (wait_data_dma_axi4_cpu_m_event),
  .emit_req_7           (emit_req_dma_axi4_cpu_m_event),
  .emit_ack_7           (emit_ack_dma_axi4_cpu_m_event),
  .emit_data_7          (emit_data_dma_axi4_cpu_m_event),
  .wait_req_8           (wait_req_sram_slv_axi4_event),
  .wait_ack_8           (wait_ack_sram_slv_axi4_event),
  .wait_data_8          (wait_data_sram_slv_axi4_event),
  .emit_req_8           (emit_req_sram_slv_axi4_event),
  .emit_ack_8           (emit_ack_sram_slv_axi4_event),
  .emit_data_8          (emit_data_sram_slv_axi4_event),
  .wait_req_9           (wait_req_psram_slv_axi4_event),
  .wait_ack_9           (wait_ack_psram_slv_axi4_event),
  .wait_data_9          (wait_data_psram_slv_axi4_event),
  .emit_req_9           (emit_req_psram_slv_axi4_event),
  .emit_ack_9           (emit_ack_psram_slv_axi4_event),
  .emit_data_9          (emit_data_psram_slv_axi4_event),
  .pclk                 (clk_tb),
  .presetn              (resetn_tb)
);


apb4_s_if     archinfo_slv_apb4 (
  .PADDR                (paddr_archinfo_slv_apb4),
  .PWDATA               (pwdata_archinfo_slv_apb4),
  .PWRITE               (pwrite_archinfo_slv_apb4),
  .PENABLE              (penable_archinfo_slv_apb4),
  .PSEL                 (pselx_archinfo_slv_apb4),
  .PRDATA               (prdata_archinfo_slv_apb4),
  .PSLVERR              (pslverr_archinfo_slv_apb4),
  .PREADY               (pready_archinfo_slv_apb4),
  .PPROT                (pprot_archinfo_slv_apb4),
  .PSTRB                (pstrb_archinfo_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam archinfo_slv_apb4.APB_TYPE = 4;
defparam archinfo_slv_apb4.ID_WIDTH = 4;
defparam archinfo_slv_apb4.INSTANCE = "archinfo_slv_apb4";


axi4_s_if     chiplink_slv_axi4_tpv (
  .WAIT_REQ             (wait_req_chiplink_slv_axi4_tpv_event),
  .WAIT_ACK             (wait_ack_chiplink_slv_axi4_tpv_event),
  .WAIT_DATA            (wait_data_chiplink_slv_axi4_tpv_event),
  .EMIT_REQ             (emit_req_chiplink_slv_axi4_tpv_event),
  .EMIT_ACK             (emit_ack_chiplink_slv_axi4_tpv_event),
  .EMIT_DATA            (emit_data_chiplink_slv_axi4_tpv_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_chiplink_slv_axi4_tpv_apb),
  .PRDATA               (prdata_chiplink_slv_axi4_tpv_apb),
  .PSLVERR              (pslverr_chiplink_slv_axi4_tpv_apb),
  .PREADY               (pready_chiplink_slv_axi4_tpv_apb),
  .ACLK                 (clk_peri_25mclk),
  .ARESETn              (clk_peri_25mresetn),
  .AWID                 (awid_chiplink_slv_axi4_tpv),
  .AWADDR               (awaddr_chiplink_slv_axi4_tpv),
  .AWLEN                (awlen_chiplink_slv_axi4_tpv),
  .AWQOS                (4'b0),
  .AWSIZE               (awsize_chiplink_slv_axi4_tpv),
  .AWBURST              (awburst_chiplink_slv_axi4_tpv),
  .AWLOCK               (awlock_chiplink_slv_axi4_tpv),
  .AWCACHE              (awcache_chiplink_slv_axi4_tpv),
  .AWPROT               (awprot_chiplink_slv_axi4_tpv),
  .AWVALID              (awvalid_chiplink_slv_axi4_tpv),
  .AWREGION             (4'b0),
  .AWREADY              (awready_chiplink_slv_axi4_tpv),
  .WDATA                (wdata_chiplink_slv_axi4_tpv),
  .WSTRB                (wstrb_chiplink_slv_axi4_tpv),
  .WLAST                (wlast_chiplink_slv_axi4_tpv),
  .WVALID               (wvalid_chiplink_slv_axi4_tpv),
  .WREADY               (wready_chiplink_slv_axi4_tpv),
  .BID                  (bid_chiplink_slv_axi4_tpv),
  .BRESP                (bresp_chiplink_slv_axi4_tpv),
  .BVALID               (bvalid_chiplink_slv_axi4_tpv),
  .BREADY               (bready_chiplink_slv_axi4_tpv),
  .ARID                 (arid_chiplink_slv_axi4_tpv),
  .ARADDR               (araddr_chiplink_slv_axi4_tpv),
  .ARLEN                (arlen_chiplink_slv_axi4_tpv),
  .ARQOS                (4'b0),
  .ARSIZE               (arsize_chiplink_slv_axi4_tpv),
  .ARBURST              (arburst_chiplink_slv_axi4_tpv),
  .ARLOCK               (arlock_chiplink_slv_axi4_tpv),
  .ARCACHE              (arcache_chiplink_slv_axi4_tpv),
  .ARPROT               (arprot_chiplink_slv_axi4_tpv),
  .ARVALID              (arvalid_chiplink_slv_axi4_tpv),
  .ARREGION             (4'b0),
  .ARREADY              (arready_chiplink_slv_axi4_tpv),
  .RID                  (rid_chiplink_slv_axi4_tpv),
  .RDATA                (rdata_chiplink_slv_axi4_tpv),
  .RRESP                (rresp_chiplink_slv_axi4_tpv),
  .RLAST                (rlast_chiplink_slv_axi4_tpv),
  .RVALID               (rvalid_chiplink_slv_axi4_tpv),
  .RREADY               (rready_chiplink_slv_axi4_tpv),
  .AWUSER               ({(chiplink_slv_axi4_tpv_AWUSER_WIDTH-1 + 1){1'b0}}),
  .WUSER                ({(chiplink_slv_axi4_tpv_WUSER_WIDTH-1 + 1){1'b0}}),
  .BUSER                (),
  .ARUSER               ({(chiplink_slv_axi4_tpv_ARUSER_WIDTH-1 + 1){1'b0}}),
  .RUSER                (),
  .ACLKEN               (1'b0)
);
defparam chiplink_slv_axi4_tpv.ADDR_WIDTH = 32;
defparam chiplink_slv_axi4_tpv.ARUSER_WIDTH = chiplink_slv_axi4_tpv_ARUSER_WIDTH;
defparam chiplink_slv_axi4_tpv.AWUSER_WIDTH = chiplink_slv_axi4_tpv_AWUSER_WIDTH;
defparam chiplink_slv_axi4_tpv.BUSER_WIDTH = chiplink_slv_axi4_tpv_BUSER_WIDTH;
defparam chiplink_slv_axi4_tpv.DATA_WIDTH = 64;
defparam chiplink_slv_axi4_tpv.DriveOnlyOnEnable = chiplink_slv_axi4_tpv_DriveOnlyOnEnable;
defparam chiplink_slv_axi4_tpv.EW_WIDTH = 16;
defparam chiplink_slv_axi4_tpv.ID_WIDTH = 4;
defparam chiplink_slv_axi4_tpv.INSTANCE = "chiplink_slv_axi4_tpv";
defparam chiplink_slv_axi4_tpv.PortIsInternal = chiplink_slv_axi4_tpv_PortIsInternal;
defparam chiplink_slv_axi4_tpv.RUSER_WIDTH = chiplink_slv_axi4_tpv_RUSER_WIDTH;
defparam chiplink_slv_axi4_tpv.STRB_WIDTH = 8;
defparam chiplink_slv_axi4_tpv.USE_X = chiplink_slv_axi4_tpv_USE_X;
defparam chiplink_slv_axi4_tpv.VALID_WIDTH = 1;
defparam chiplink_slv_axi4_tpv.WUSER_WIDTH = chiplink_slv_axi4_tpv_WUSER_WIDTH;
defparam chiplink_slv_axi4_tpv.combined_issuing_capability = chiplink_slv_axi4_tpv_combined_issuing_capability;
defparam chiplink_slv_axi4_tpv.leading_writes = chiplink_slv_axi4_tpv_leading_writes;
defparam chiplink_slv_axi4_tpv.limit_acceptance_capability = 1;
defparam chiplink_slv_axi4_tpv.read_issuing_capability = 1;
defparam chiplink_slv_axi4_tpv.regions_flag = 1;
defparam chiplink_slv_axi4_tpv.write_issuing_capability = 1;


apb4_s_if     clint_slv_apb4 (
  .PADDR                (paddr_clint_slv_apb4),
  .PWDATA               (pwdata_clint_slv_apb4),
  .PWRITE               (pwrite_clint_slv_apb4),
  .PENABLE              (penable_clint_slv_apb4),
  .PSEL                 (pselx_clint_slv_apb4),
  .PRDATA               (prdata_clint_slv_apb4),
  .PSLVERR              (pslverr_clint_slv_apb4),
  .PREADY               (pready_clint_slv_apb4),
  .PPROT                (pprot_clint_slv_apb4),
  .PSTRB                (pstrb_clint_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam clint_slv_apb4.APB_TYPE = 4;
defparam clint_slv_apb4.ID_WIDTH = 4;
defparam clint_slv_apb4.INSTANCE = "clint_slv_apb4";


clk_reset_if     clk_reset_if (
  .clk_tb               (clk_tb),
  .resetn_tb            (resetn_tb),
  .paddr                (paddr_clk_rst_apb),
  .pwdata               (pwdata_clk_rst_apb),
  .pwrite               (pwrite_clk_rst_apb),
  .penable              (penable_clk_rst_apb),
  .psel                 (pselx_clk_rst_apb),
  .prdata               (prdata_clk_rst_apb),
  .pslverr              (pslverr_clk_rst_apb),
  .pready               (pready_clk_rst_apb),
  .clk_aud_12288kclk    (),
  .clk_aud_12288kclk_tb (clk_aud_12288kclk),
  .clk_aud_12288ken     (),
  .clk_aud_12288ken_apb (clk_aud_12288kclken),
  .clk_aud_12288kresetn (clk_aud_12288kresetn),
  .clk_core_200_800mclk (),
  .clk_core_200_800mclk_r (clk_core_200_800mclk_r),
  .clk_core_200_800mclk_tb (clk_core_200_800mclk),
  .clk_core_200_800men  (),
  .clk_core_200_800men_apb (clk_core_200_800mclken),
  .clk_core_200_800mresetn (clk_core_200_800mresetn),
  .clk_core_200_800mresetn_r (clk_core_200_800mresetn_r),
  .clk_peri_100mclk     (),
  .clk_peri_100mclk_r   (clk_peri_100mclk_r),
  .clk_peri_100mclk_tb  (clk_peri_100mclk),
  .clk_peri_100men      (),
  .clk_peri_100men_apb  (clk_peri_100mclken),
  .clk_peri_100mresetn  (clk_peri_100mresetn),
  .clk_peri_100mresetn_r (clk_peri_100mresetn_r),
  .clk_peri_25mclk      (),
  .clk_peri_25mclk_r    (clk_peri_25mclk_r),
  .clk_peri_25mclk_tb   (clk_peri_25mclk),
  .clk_peri_25men       (),
  .clk_peri_25men_apb   (clk_peri_25mclken),
  .clk_peri_25mresetn   (clk_peri_25mresetn),
  .clk_peri_25mresetn_r (clk_peri_25mresetn_r)
);


config_if     config_if (
  .WAIT_REQ             (wait_req_cfg_event),
  .WAIT_ACK             (wait_ack_cfg_event),
  .WAIT_DATA            (wait_data_cfg_event),
  .EMIT_REQ             (emit_req_cfg_event),
  .EMIT_ACK             (emit_ack_cfg_event),
  .EMIT_DATA            (emit_data_cfg_event),
  .PSEL                 (pselx_clk_rst_apb),
  .PRDATA               (prdata_clk_rst_apb),
  .PSLVERR              (pslverr_clk_rst_apb),
  .PREADY               (pready_clk_rst_apb),
  .PSEL_1               (pselx_cpu_mst_axi4_apb),
  .PRDATA_1             (prdata_cpu_mst_axi4_apb),
  .PSLVERR_1            (pslverr_cpu_mst_axi4_apb),
  .PREADY_1             (pready_cpu_mst_axi4_apb),
  .PSEL_2               (pselx_dma_axi4_cpu_s_apb),
  .PRDATA_2             (prdata_dma_axi4_cpu_s_apb),
  .PSLVERR_2            (pslverr_dma_axi4_cpu_s_apb),
  .PREADY_2             (pready_dma_axi4_cpu_s_apb),
  .PSEL_3               (pselx_vgalcd_mst_axi4_apb),
  .PRDATA_3             (prdata_vgalcd_mst_axi4_apb),
  .PSLVERR_3            (pslverr_vgalcd_mst_axi4_apb),
  .PREADY_3             (pready_vgalcd_mst_axi4_apb),
  .PSEL_4               (pselx_chiplink_slv_axi4_tpv_apb),
  .PRDATA_4             (prdata_chiplink_slv_axi4_tpv_apb),
  .PSLVERR_4            (pslverr_chiplink_slv_axi4_tpv_apb),
  .PREADY_4             (pready_chiplink_slv_axi4_tpv_apb),
  .PSEL_5               (pselx_sdram_slv_axi4_apb),
  .PRDATA_5             (prdata_sdram_slv_axi4_apb),
  .PSLVERR_5            (pslverr_sdram_slv_axi4_apb),
  .PREADY_5             (pready_sdram_slv_axi4_apb),
  .PSEL_6               (pselx_dma_axi4_cpu_m_apb),
  .PRDATA_6             (prdata_dma_axi4_cpu_m_apb),
  .PSLVERR_6            (pslverr_dma_axi4_cpu_m_apb),
  .PREADY_6             (pready_dma_axi4_cpu_m_apb),
  .PSEL_7               (pselx_sram_slv_axi4_apb),
  .PRDATA_7             (prdata_sram_slv_axi4_apb),
  .PSLVERR_7            (pslverr_sram_slv_axi4_apb),
  .PREADY_7             (pready_sram_slv_axi4_apb),
  .PADDR                (paddr_clk_rst_apb),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL_8               (pselx_psram_slv_axi4_apb),
  .PRDATA_8             (prdata_psram_slv_axi4_apb),
  .PSLVERR_8            (pslverr_psram_slv_axi4_apb),
  .PREADY_8             (pready_psram_slv_axi4_apb)
);
defparam config_if.EW_WIDTH = 16;


axi4_m_if     cpu_mst_axi4 (
  .WAIT_REQ             (wait_req_cpu_mst_axi4_event),
  .WAIT_ACK             (wait_ack_cpu_mst_axi4_event),
  .WAIT_DATA            (wait_data_cpu_mst_axi4_event),
  .EMIT_REQ             (emit_req_cpu_mst_axi4_event),
  .EMIT_ACK             (emit_ack_cpu_mst_axi4_event),
  .EMIT_DATA            (emit_data_cpu_mst_axi4_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_cpu_mst_axi4_apb),
  .PRDATA               (prdata_cpu_mst_axi4_apb),
  .PSLVERR              (pslverr_cpu_mst_axi4_apb),
  .PREADY               (pready_cpu_mst_axi4_apb),
  .ACLK                 (clk_core_200_800mclk),
  .ARESETn              (clk_core_200_800mresetn),
  .AWID                 (awid_cpu_mst_axi4_data),
  .AWADDR               (awaddr_cpu_mst_axi4_data),
  .AWLEN                (awlen_cpu_mst_axi4_data),
  .AWQOS                (),
  .AWSIZE               (awsize_cpu_mst_axi4_data),
  .AWBURST              (awburst_cpu_mst_axi4_data),
  .AWLOCK               (awlock_cpu_mst_axi4_data),
  .AWCACHE              (awcache_cpu_mst_axi4_data),
  .AWPROT               (awprot_cpu_mst_axi4_data),
  .AWVALID              (awvalid_cpu_mst_axi4_data),
  .AWREGION             (),
  .AWREADY              (awready_cpu_mst_axi4_data),
  .WDATA                (wdata_cpu_mst_axi4_data),
  .WSTRB                (wstrb_cpu_mst_axi4_data),
  .WLAST                (wlast_cpu_mst_axi4_data),
  .WVALID               (wvalid_cpu_mst_axi4_data),
  .WREADY               (wready_cpu_mst_axi4_data),
  .BID                  (bid_cpu_mst_axi4_data),
  .BRESP                (bresp_cpu_mst_axi4_data),
  .BVALID               (bvalid_cpu_mst_axi4_data),
  .BREADY               (bready_cpu_mst_axi4_data),
  .ARID                 (arid_cpu_mst_axi4_data),
  .ARADDR               (araddr_cpu_mst_axi4_data),
  .ARLEN                (arlen_cpu_mst_axi4_data),
  .ARQOS                (),
  .ARSIZE               (arsize_cpu_mst_axi4_data),
  .ARBURST              (arburst_cpu_mst_axi4_data),
  .ARLOCK               (arlock_cpu_mst_axi4_data),
  .ARCACHE              (arcache_cpu_mst_axi4_data),
  .ARPROT               (arprot_cpu_mst_axi4_data),
  .ARVALID              (arvalid_cpu_mst_axi4_data),
  .ARREGION             (),
  .ARREADY              (arready_cpu_mst_axi4_data),
  .RID                  (rid_cpu_mst_axi4_data),
  .RDATA                (rdata_cpu_mst_axi4_data),
  .RRESP                (rresp_cpu_mst_axi4_data),
  .RLAST                (rlast_cpu_mst_axi4_data),
  .RVALID               (rvalid_cpu_mst_axi4_data),
  .RREADY               (rready_cpu_mst_axi4_data),
  .AWUSER               (),
  .WUSER                (),
  .BUSER                ({(cpu_mst_axi4_BUSER_WIDTH-1 + 1){1'b0}}),
  .ARUSER               (),
  .RUSER                ({(cpu_mst_axi4_RUSER_WIDTH-1 + 1){1'b0}}),
  .ACLKEN               (1'b0)
);
defparam cpu_mst_axi4.ADDR_WIDTH = 32;
defparam cpu_mst_axi4.ARUSER_WIDTH = cpu_mst_axi4_ARUSER_WIDTH;
defparam cpu_mst_axi4.AWUSER_WIDTH = cpu_mst_axi4_AWUSER_WIDTH;
defparam cpu_mst_axi4.BUSER_WIDTH = cpu_mst_axi4_BUSER_WIDTH;
defparam cpu_mst_axi4.DATA_WIDTH = 32;
defparam cpu_mst_axi4.DriveOnlyOnEnable = cpu_mst_axi4_DriveOnlyOnEnable;
defparam cpu_mst_axi4.EW_WIDTH = 16;
defparam cpu_mst_axi4.ID_WIDTH = 3;
defparam cpu_mst_axi4.INSTANCE = "cpu_mst_axi4";
defparam cpu_mst_axi4.MaxWaits = cpu_mst_axi4_MaxWaits;
defparam cpu_mst_axi4.PortIsInternal = cpu_mst_axi4_PortIsInternal;
defparam cpu_mst_axi4.RUSER_WIDTH = cpu_mst_axi4_RUSER_WIDTH;
defparam cpu_mst_axi4.RecMaxWaitOn = cpu_mst_axi4_RecMaxWaitOn;
defparam cpu_mst_axi4.RecommendOn = cpu_mst_axi4_RecommendOn;
defparam cpu_mst_axi4.STRB_WIDTH = 4;
defparam cpu_mst_axi4.USE_X = cpu_mst_axi4_USE_X;
defparam cpu_mst_axi4.VALID_WIDTH = 1;
defparam cpu_mst_axi4.WUSER_WIDTH = cpu_mst_axi4_WUSER_WIDTH;
defparam cpu_mst_axi4.leading_write_depth = cpu_mst_axi4_leading_write_depth;
defparam cpu_mst_axi4.limit_issuing_capability = 0;
defparam cpu_mst_axi4.read_acceptance_capability = cpu_mst_axi4_read_acceptance_capability;
defparam cpu_mst_axi4.unlimited_acceptance_capability = 0;
defparam cpu_mst_axi4.write_acceptance_capability = cpu_mst_axi4_write_acceptance_capability;


apb4_s_if     crc_slv_apb4 (
  .PADDR                (paddr_crc_slv_apb4),
  .PWDATA               (pwdata_crc_slv_apb4),
  .PWRITE               (pwrite_crc_slv_apb4),
  .PENABLE              (penable_crc_slv_apb4),
  .PSEL                 (pselx_crc_slv_apb4),
  .PRDATA               (prdata_crc_slv_apb4),
  .PSLVERR              (pslverr_crc_slv_apb4),
  .PREADY               (pready_crc_slv_apb4),
  .PPROT                (pprot_crc_slv_apb4),
  .PSTRB                (pstrb_crc_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam crc_slv_apb4.APB_TYPE = 4;
defparam crc_slv_apb4.ID_WIDTH = 4;
defparam crc_slv_apb4.INSTANCE = "crc_slv_apb4";


axi4_s_if     dma_axi4_cpu_m (
  .WAIT_REQ             (wait_req_dma_axi4_cpu_m_event),
  .WAIT_ACK             (wait_ack_dma_axi4_cpu_m_event),
  .WAIT_DATA            (wait_data_dma_axi4_cpu_m_event),
  .EMIT_REQ             (emit_req_dma_axi4_cpu_m_event),
  .EMIT_ACK             (emit_ack_dma_axi4_cpu_m_event),
  .EMIT_DATA            (emit_data_dma_axi4_cpu_m_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_dma_axi4_cpu_m_apb),
  .PRDATA               (prdata_dma_axi4_cpu_m_apb),
  .PSLVERR              (pslverr_dma_axi4_cpu_m_apb),
  .PREADY               (pready_dma_axi4_cpu_m_apb),
  .ACLK                 (clk_core_200_800mclk),
  .ARESETn              (clk_core_200_800mresetn),
  .AWID                 (awid_dma_axi4_cpu_m),
  .AWADDR               (awaddr_dma_axi4_cpu_m),
  .AWLEN                (awlen_dma_axi4_cpu_m),
  .AWQOS                (4'b0),
  .AWSIZE               (awsize_dma_axi4_cpu_m),
  .AWBURST              (awburst_dma_axi4_cpu_m),
  .AWLOCK               (awlock_dma_axi4_cpu_m),
  .AWCACHE              (awcache_dma_axi4_cpu_m),
  .AWPROT               (awprot_dma_axi4_cpu_m),
  .AWVALID              (awvalid_dma_axi4_cpu_m),
  .AWREGION             (4'b0),
  .AWREADY              (awready_dma_axi4_cpu_m),
  .WDATA                (wdata_dma_axi4_cpu_m),
  .WSTRB                (wstrb_dma_axi4_cpu_m),
  .WLAST                (wlast_dma_axi4_cpu_m),
  .WVALID               (wvalid_dma_axi4_cpu_m),
  .WREADY               (wready_dma_axi4_cpu_m),
  .BID                  (bid_dma_axi4_cpu_m),
  .BRESP                (bresp_dma_axi4_cpu_m),
  .BVALID               (bvalid_dma_axi4_cpu_m),
  .BREADY               (bready_dma_axi4_cpu_m),
  .ARID                 (arid_dma_axi4_cpu_m),
  .ARADDR               (araddr_dma_axi4_cpu_m),
  .ARLEN                (arlen_dma_axi4_cpu_m),
  .ARQOS                (4'b0),
  .ARSIZE               (arsize_dma_axi4_cpu_m),
  .ARBURST              (arburst_dma_axi4_cpu_m),
  .ARLOCK               (arlock_dma_axi4_cpu_m),
  .ARCACHE              (arcache_dma_axi4_cpu_m),
  .ARPROT               (arprot_dma_axi4_cpu_m),
  .ARVALID              (arvalid_dma_axi4_cpu_m),
  .ARREGION             (4'b0),
  .ARREADY              (arready_dma_axi4_cpu_m),
  .RID                  (rid_dma_axi4_cpu_m),
  .RDATA                (rdata_dma_axi4_cpu_m),
  .RRESP                (rresp_dma_axi4_cpu_m),
  .RLAST                (rlast_dma_axi4_cpu_m),
  .RVALID               (rvalid_dma_axi4_cpu_m),
  .RREADY               (rready_dma_axi4_cpu_m),
  .AWUSER               ({(dma_axi4_cpu_m_AWUSER_WIDTH-1 + 1){1'b0}}),
  .WUSER                ({(dma_axi4_cpu_m_WUSER_WIDTH-1 + 1){1'b0}}),
  .BUSER                (),
  .ARUSER               ({(dma_axi4_cpu_m_ARUSER_WIDTH-1 + 1){1'b0}}),
  .RUSER                (),
  .ACLKEN               (1'b0)
);
defparam dma_axi4_cpu_m.ADDR_WIDTH = 32;
defparam dma_axi4_cpu_m.ARUSER_WIDTH = dma_axi4_cpu_m_ARUSER_WIDTH;
defparam dma_axi4_cpu_m.AWUSER_WIDTH = dma_axi4_cpu_m_AWUSER_WIDTH;
defparam dma_axi4_cpu_m.BUSER_WIDTH = dma_axi4_cpu_m_BUSER_WIDTH;
defparam dma_axi4_cpu_m.DATA_WIDTH = 32;
defparam dma_axi4_cpu_m.DriveOnlyOnEnable = dma_axi4_cpu_m_DriveOnlyOnEnable;
defparam dma_axi4_cpu_m.EW_WIDTH = 16;
defparam dma_axi4_cpu_m.ID_WIDTH = 4;
defparam dma_axi4_cpu_m.INSTANCE = "dma_axi4_cpu_m";
defparam dma_axi4_cpu_m.PortIsInternal = dma_axi4_cpu_m_PortIsInternal;
defparam dma_axi4_cpu_m.RUSER_WIDTH = dma_axi4_cpu_m_RUSER_WIDTH;
defparam dma_axi4_cpu_m.STRB_WIDTH = 4;
defparam dma_axi4_cpu_m.USE_X = dma_axi4_cpu_m_USE_X;
defparam dma_axi4_cpu_m.VALID_WIDTH = 1;
defparam dma_axi4_cpu_m.WUSER_WIDTH = dma_axi4_cpu_m_WUSER_WIDTH;
defparam dma_axi4_cpu_m.combined_issuing_capability = dma_axi4_cpu_m_combined_issuing_capability;
defparam dma_axi4_cpu_m.leading_writes = dma_axi4_cpu_m_leading_writes;
defparam dma_axi4_cpu_m.limit_acceptance_capability = 1;
defparam dma_axi4_cpu_m.read_issuing_capability = 1;
defparam dma_axi4_cpu_m.regions_flag = 1;
defparam dma_axi4_cpu_m.write_issuing_capability = 1;


axi4_m_if     dma_axi4_cpu_s (
  .WAIT_REQ             (wait_req_dma_axi4_cpu_s_event),
  .WAIT_ACK             (wait_ack_dma_axi4_cpu_s_event),
  .WAIT_DATA            (wait_data_dma_axi4_cpu_s_event),
  .EMIT_REQ             (emit_req_dma_axi4_cpu_s_event),
  .EMIT_ACK             (emit_ack_dma_axi4_cpu_s_event),
  .EMIT_DATA            (emit_data_dma_axi4_cpu_s_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_dma_axi4_cpu_s_apb),
  .PRDATA               (prdata_dma_axi4_cpu_s_apb),
  .PSLVERR              (pslverr_dma_axi4_cpu_s_apb),
  .PREADY               (pready_dma_axi4_cpu_s_apb),
  .ACLK                 (clk_peri_25mclk),
  .ARESETn              (clk_peri_25mresetn),
  .AWID                 (awid_dma_axi4_cpu_s_data),
  .AWADDR               (awaddr_dma_axi4_cpu_s_data),
  .AWLEN                (awlen_dma_axi4_cpu_s_data),
  .AWQOS                (),
  .AWSIZE               (awsize_dma_axi4_cpu_s_data),
  .AWBURST              (awburst_dma_axi4_cpu_s_data),
  .AWLOCK               (awlock_dma_axi4_cpu_s_data),
  .AWCACHE              (awcache_dma_axi4_cpu_s_data),
  .AWPROT               (awprot_dma_axi4_cpu_s_data),
  .AWVALID              (awvalid_dma_axi4_cpu_s_data),
  .AWREGION             (),
  .AWREADY              (awready_dma_axi4_cpu_s_data),
  .WDATA                (wdata_dma_axi4_cpu_s_data),
  .WSTRB                (wstrb_dma_axi4_cpu_s_data),
  .WLAST                (wlast_dma_axi4_cpu_s_data),
  .WVALID               (wvalid_dma_axi4_cpu_s_data),
  .WREADY               (wready_dma_axi4_cpu_s_data),
  .BID                  (bid_dma_axi4_cpu_s_data),
  .BRESP                (bresp_dma_axi4_cpu_s_data),
  .BVALID               (bvalid_dma_axi4_cpu_s_data),
  .BREADY               (bready_dma_axi4_cpu_s_data),
  .ARID                 (arid_dma_axi4_cpu_s_data),
  .ARADDR               (araddr_dma_axi4_cpu_s_data),
  .ARLEN                (arlen_dma_axi4_cpu_s_data),
  .ARQOS                (),
  .ARSIZE               (arsize_dma_axi4_cpu_s_data),
  .ARBURST              (arburst_dma_axi4_cpu_s_data),
  .ARLOCK               (arlock_dma_axi4_cpu_s_data),
  .ARCACHE              (arcache_dma_axi4_cpu_s_data),
  .ARPROT               (arprot_dma_axi4_cpu_s_data),
  .ARVALID              (arvalid_dma_axi4_cpu_s_data),
  .ARREGION             (),
  .ARREADY              (arready_dma_axi4_cpu_s_data),
  .RID                  (rid_dma_axi4_cpu_s_data),
  .RDATA                (rdata_dma_axi4_cpu_s_data),
  .RRESP                (rresp_dma_axi4_cpu_s_data),
  .RLAST                (rlast_dma_axi4_cpu_s_data),
  .RVALID               (rvalid_dma_axi4_cpu_s_data),
  .RREADY               (rready_dma_axi4_cpu_s_data),
  .AWUSER               (),
  .WUSER                (),
  .BUSER                ({(dma_axi4_cpu_s_BUSER_WIDTH-1 + 1){1'b0}}),
  .ARUSER               (),
  .RUSER                ({(dma_axi4_cpu_s_RUSER_WIDTH-1 + 1){1'b0}}),
  .ACLKEN               (1'b0)
);
defparam dma_axi4_cpu_s.ADDR_WIDTH = 32;
defparam dma_axi4_cpu_s.ARUSER_WIDTH = dma_axi4_cpu_s_ARUSER_WIDTH;
defparam dma_axi4_cpu_s.AWUSER_WIDTH = dma_axi4_cpu_s_AWUSER_WIDTH;
defparam dma_axi4_cpu_s.BUSER_WIDTH = dma_axi4_cpu_s_BUSER_WIDTH;
defparam dma_axi4_cpu_s.DATA_WIDTH = 64;
defparam dma_axi4_cpu_s.DriveOnlyOnEnable = dma_axi4_cpu_s_DriveOnlyOnEnable;
defparam dma_axi4_cpu_s.EW_WIDTH = 16;
defparam dma_axi4_cpu_s.ID_WIDTH = 4;
defparam dma_axi4_cpu_s.INSTANCE = "dma_axi4_cpu_s";
defparam dma_axi4_cpu_s.MaxWaits = dma_axi4_cpu_s_MaxWaits;
defparam dma_axi4_cpu_s.PortIsInternal = dma_axi4_cpu_s_PortIsInternal;
defparam dma_axi4_cpu_s.RUSER_WIDTH = dma_axi4_cpu_s_RUSER_WIDTH;
defparam dma_axi4_cpu_s.RecMaxWaitOn = dma_axi4_cpu_s_RecMaxWaitOn;
defparam dma_axi4_cpu_s.RecommendOn = dma_axi4_cpu_s_RecommendOn;
defparam dma_axi4_cpu_s.STRB_WIDTH = 8;
defparam dma_axi4_cpu_s.USE_X = dma_axi4_cpu_s_USE_X;
defparam dma_axi4_cpu_s.VALID_WIDTH = 1;
defparam dma_axi4_cpu_s.WUSER_WIDTH = dma_axi4_cpu_s_WUSER_WIDTH;
defparam dma_axi4_cpu_s.leading_write_depth = dma_axi4_cpu_s_leading_write_depth;
defparam dma_axi4_cpu_s.limit_issuing_capability = 1;
defparam dma_axi4_cpu_s.read_acceptance_capability = dma_axi4_cpu_s_read_acceptance_capability;
defparam dma_axi4_cpu_s.unlimited_acceptance_capability = 0;
defparam dma_axi4_cpu_s.write_acceptance_capability = dma_axi4_cpu_s_write_acceptance_capability;


apb4_s_if     gpio_slv_apb4 (
  .PADDR                (paddr_gpio_slv_apb4),
  .PWDATA               (pwdata_gpio_slv_apb4),
  .PWRITE               (pwrite_gpio_slv_apb4),
  .PENABLE              (penable_gpio_slv_apb4),
  .PSEL                 (pselx_gpio_slv_apb4),
  .PRDATA               (prdata_gpio_slv_apb4),
  .PSLVERR              (pslverr_gpio_slv_apb4),
  .PREADY               (pready_gpio_slv_apb4),
  .PPROT                (pprot_gpio_slv_apb4),
  .PSTRB                (pstrb_gpio_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam gpio_slv_apb4.APB_TYPE = 4;
defparam gpio_slv_apb4.ID_WIDTH = 4;
defparam gpio_slv_apb4.INSTANCE = "gpio_slv_apb4";


apb4_s_if     i2c_slv_apb4 (
  .PADDR                (paddr_i2c_slv_apb4),
  .PWDATA               (pwdata_i2c_slv_apb4),
  .PWRITE               (pwrite_i2c_slv_apb4),
  .PENABLE              (penable_i2c_slv_apb4),
  .PSEL                 (pselx_i2c_slv_apb4),
  .PRDATA               (prdata_i2c_slv_apb4),
  .PSLVERR              (pslverr_i2c_slv_apb4),
  .PREADY               (pready_i2c_slv_apb4),
  .PPROT                (pprot_i2c_slv_apb4),
  .PSTRB                (pstrb_i2c_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam i2c_slv_apb4.APB_TYPE = 4;
defparam i2c_slv_apb4.ID_WIDTH = 4;
defparam i2c_slv_apb4.INSTANCE = "i2c_slv_apb4";


apb4_s_if     i2s_slv_apb4 (
  .PADDR                (paddr_i2s_slv_apb4),
  .PWDATA               (pwdata_i2s_slv_apb4),
  .PWRITE               (pwrite_i2s_slv_apb4),
  .PENABLE              (penable_i2s_slv_apb4),
  .PSEL                 (pselx_i2s_slv_apb4),
  .PRDATA               (prdata_i2s_slv_apb4),
  .PSLVERR              (pslverr_i2s_slv_apb4),
  .PREADY               (pready_i2s_slv_apb4),
  .PPROT                (pprot_i2s_slv_apb4),
  .PSTRB                (pstrb_i2s_slv_apb4),
  .PCLK                 (clk_aud_12288kclk),
  .PCLKEN               (clk_aud_12288kclken),
  .presetn              (clk_aud_12288kresetn)
);
defparam i2s_slv_apb4.APB_TYPE = 4;
defparam i2s_slv_apb4.ID_WIDTH = 4;
defparam i2s_slv_apb4.INSTANCE = "i2s_slv_apb4";


apb4_s_if     plic_slv_apb4 (
  .PADDR                (paddr_plic_slv_apb4),
  .PWDATA               (pwdata_plic_slv_apb4),
  .PWRITE               (pwrite_plic_slv_apb4),
  .PENABLE              (penable_plic_slv_apb4),
  .PSEL                 (pselx_plic_slv_apb4),
  .PRDATA               (prdata_plic_slv_apb4),
  .PSLVERR              (pslverr_plic_slv_apb4),
  .PREADY               (pready_plic_slv_apb4),
  .PPROT                (pprot_plic_slv_apb4),
  .PSTRB                (pstrb_plic_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam plic_slv_apb4.APB_TYPE = 4;
defparam plic_slv_apb4.ID_WIDTH = 4;
defparam plic_slv_apb4.INSTANCE = "plic_slv_apb4";


apb4_s_if     ps2_slv_apb4 (
  .PADDR                (paddr_ps2_slv_apb4),
  .PWDATA               (pwdata_ps2_slv_apb4),
  .PWRITE               (pwrite_ps2_slv_apb4),
  .PENABLE              (penable_ps2_slv_apb4),
  .PSEL                 (pselx_ps2_slv_apb4),
  .PRDATA               (prdata_ps2_slv_apb4),
  .PSLVERR              (pslverr_ps2_slv_apb4),
  .PREADY               (pready_ps2_slv_apb4),
  .PPROT                (pprot_ps2_slv_apb4),
  .PSTRB                (pstrb_ps2_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam ps2_slv_apb4.APB_TYPE = 4;
defparam ps2_slv_apb4.ID_WIDTH = 4;
defparam ps2_slv_apb4.INSTANCE = "ps2_slv_apb4";


apb4_s_if     psram_slv_apb4 (
  .PADDR                (paddr_psram_slv_apb4),
  .PWDATA               (pwdata_psram_slv_apb4),
  .PWRITE               (pwrite_psram_slv_apb4),
  .PENABLE              (penable_psram_slv_apb4),
  .PSEL                 (pselx_psram_slv_apb4),
  .PRDATA               (prdata_psram_slv_apb4),
  .PSLVERR              (pslverr_psram_slv_apb4),
  .PREADY               (pready_psram_slv_apb4),
  .PPROT                (pprot_psram_slv_apb4),
  .PSTRB                (pstrb_psram_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam psram_slv_apb4.APB_TYPE = 4;
defparam psram_slv_apb4.ID_WIDTH = 4;
defparam psram_slv_apb4.INSTANCE = "psram_slv_apb4";


axi4_s_if     psram_slv_axi4 (
  .WAIT_REQ             (wait_req_psram_slv_axi4_event),
  .WAIT_ACK             (wait_ack_psram_slv_axi4_event),
  .WAIT_DATA            (wait_data_psram_slv_axi4_event),
  .EMIT_REQ             (emit_req_psram_slv_axi4_event),
  .EMIT_ACK             (emit_ack_psram_slv_axi4_event),
  .EMIT_DATA            (emit_data_psram_slv_axi4_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_psram_slv_axi4_apb),
  .PRDATA               (prdata_psram_slv_axi4_apb),
  .PSLVERR              (pslverr_psram_slv_axi4_apb),
  .PREADY               (pready_psram_slv_axi4_apb),
  .ACLK                 (clk_peri_100mclk),
  .ARESETn              (clk_peri_100mresetn),
  .AWID                 (awid_psram_slv_axi4),
  .AWADDR               (awaddr_psram_slv_axi4),
  .AWLEN                (awlen_psram_slv_axi4),
  .AWQOS                (4'b0),
  .AWSIZE               (awsize_psram_slv_axi4),
  .AWBURST              (awburst_psram_slv_axi4),
  .AWLOCK               (awlock_psram_slv_axi4),
  .AWCACHE              (awcache_psram_slv_axi4),
  .AWPROT               (awprot_psram_slv_axi4),
  .AWVALID              (awvalid_psram_slv_axi4),
  .AWREGION             (4'b0),
  .AWREADY              (awready_psram_slv_axi4),
  .WDATA                (wdata_psram_slv_axi4),
  .WSTRB                (wstrb_psram_slv_axi4),
  .WLAST                (wlast_psram_slv_axi4),
  .WVALID               (wvalid_psram_slv_axi4),
  .WREADY               (wready_psram_slv_axi4),
  .BID                  (bid_psram_slv_axi4),
  .BRESP                (bresp_psram_slv_axi4),
  .BVALID               (bvalid_psram_slv_axi4),
  .BREADY               (bready_psram_slv_axi4),
  .ARID                 (arid_psram_slv_axi4),
  .ARADDR               (araddr_psram_slv_axi4),
  .ARLEN                (arlen_psram_slv_axi4),
  .ARQOS                (4'b0),
  .ARSIZE               (arsize_psram_slv_axi4),
  .ARBURST              (arburst_psram_slv_axi4),
  .ARLOCK               (arlock_psram_slv_axi4),
  .ARCACHE              (arcache_psram_slv_axi4),
  .ARPROT               (arprot_psram_slv_axi4),
  .ARVALID              (arvalid_psram_slv_axi4),
  .ARREGION             (4'b0),
  .ARREADY              (arready_psram_slv_axi4),
  .RID                  (rid_psram_slv_axi4),
  .RDATA                (rdata_psram_slv_axi4),
  .RRESP                (rresp_psram_slv_axi4),
  .RLAST                (rlast_psram_slv_axi4),
  .RVALID               (rvalid_psram_slv_axi4),
  .RREADY               (rready_psram_slv_axi4),
  .AWUSER               ({(psram_slv_axi4_AWUSER_WIDTH-1 + 1){1'b0}}),
  .WUSER                ({(psram_slv_axi4_WUSER_WIDTH-1 + 1){1'b0}}),
  .BUSER                (),
  .ARUSER               ({(psram_slv_axi4_ARUSER_WIDTH-1 + 1){1'b0}}),
  .RUSER                (),
  .ACLKEN               (1'b0)
);
defparam psram_slv_axi4.ADDR_WIDTH = 32;
defparam psram_slv_axi4.ARUSER_WIDTH = psram_slv_axi4_ARUSER_WIDTH;
defparam psram_slv_axi4.AWUSER_WIDTH = psram_slv_axi4_AWUSER_WIDTH;
defparam psram_slv_axi4.BUSER_WIDTH = psram_slv_axi4_BUSER_WIDTH;
defparam psram_slv_axi4.DATA_WIDTH = 64;
defparam psram_slv_axi4.DriveOnlyOnEnable = psram_slv_axi4_DriveOnlyOnEnable;
defparam psram_slv_axi4.EW_WIDTH = 16;
defparam psram_slv_axi4.ID_WIDTH = 4;
defparam psram_slv_axi4.INSTANCE = "psram_slv_axi4";
defparam psram_slv_axi4.PortIsInternal = psram_slv_axi4_PortIsInternal;
defparam psram_slv_axi4.RUSER_WIDTH = psram_slv_axi4_RUSER_WIDTH;
defparam psram_slv_axi4.STRB_WIDTH = 8;
defparam psram_slv_axi4.USE_X = psram_slv_axi4_USE_X;
defparam psram_slv_axi4.VALID_WIDTH = 1;
defparam psram_slv_axi4.WUSER_WIDTH = psram_slv_axi4_WUSER_WIDTH;
defparam psram_slv_axi4.combined_issuing_capability = psram_slv_axi4_combined_issuing_capability;
defparam psram_slv_axi4.leading_writes = psram_slv_axi4_leading_writes;
defparam psram_slv_axi4.limit_acceptance_capability = 1;
defparam psram_slv_axi4.read_issuing_capability = 1;
defparam psram_slv_axi4.regions_flag = 1;
defparam psram_slv_axi4.write_issuing_capability = 1;


apb4_s_if     pwm0_slv_apb4 (
  .PADDR                (paddr_pwm0_slv_apb4),
  .PWDATA               (pwdata_pwm0_slv_apb4),
  .PWRITE               (pwrite_pwm0_slv_apb4),
  .PENABLE              (penable_pwm0_slv_apb4),
  .PSEL                 (pselx_pwm0_slv_apb4),
  .PRDATA               (prdata_pwm0_slv_apb4),
  .PSLVERR              (pslverr_pwm0_slv_apb4),
  .PREADY               (pready_pwm0_slv_apb4),
  .PPROT                (pprot_pwm0_slv_apb4),
  .PSTRB                (pstrb_pwm0_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam pwm0_slv_apb4.APB_TYPE = 4;
defparam pwm0_slv_apb4.ID_WIDTH = 4;
defparam pwm0_slv_apb4.INSTANCE = "pwm0_slv_apb4";


apb4_s_if     pwm1_slv_apb4 (
  .PADDR                (paddr_pwm1_slv_apb4),
  .PWDATA               (pwdata_pwm1_slv_apb4),
  .PWRITE               (pwrite_pwm1_slv_apb4),
  .PENABLE              (penable_pwm1_slv_apb4),
  .PSEL                 (pselx_pwm1_slv_apb4),
  .PRDATA               (prdata_pwm1_slv_apb4),
  .PSLVERR              (pslverr_pwm1_slv_apb4),
  .PREADY               (pready_pwm1_slv_apb4),
  .PPROT                (pprot_pwm1_slv_apb4),
  .PSTRB                (pstrb_pwm1_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam pwm1_slv_apb4.APB_TYPE = 4;
defparam pwm1_slv_apb4.ID_WIDTH = 4;
defparam pwm1_slv_apb4.INSTANCE = "pwm1_slv_apb4";


apb4_s_if     pwm2_slv_apb4 (
  .PADDR                (paddr_pwm2_slv_apb4),
  .PWDATA               (pwdata_pwm2_slv_apb4),
  .PWRITE               (pwrite_pwm2_slv_apb4),
  .PENABLE              (penable_pwm2_slv_apb4),
  .PSEL                 (pselx_pwm2_slv_apb4),
  .PRDATA               (prdata_pwm2_slv_apb4),
  .PSLVERR              (pslverr_pwm2_slv_apb4),
  .PREADY               (pready_pwm2_slv_apb4),
  .PPROT                (pprot_pwm2_slv_apb4),
  .PSTRB                (pstrb_pwm2_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam pwm2_slv_apb4.APB_TYPE = 4;
defparam pwm2_slv_apb4.ID_WIDTH = 4;
defparam pwm2_slv_apb4.INSTANCE = "pwm2_slv_apb4";


apb4_s_if     qspi_slv_apb4 (
  .PADDR                (paddr_qspi_slv_apb4),
  .PWDATA               (pwdata_qspi_slv_apb4),
  .PWRITE               (pwrite_qspi_slv_apb4),
  .PENABLE              (penable_qspi_slv_apb4),
  .PSEL                 (pselx_qspi_slv_apb4),
  .PRDATA               (prdata_qspi_slv_apb4),
  .PSLVERR              (pslverr_qspi_slv_apb4),
  .PREADY               (pready_qspi_slv_apb4),
  .PPROT                (pprot_qspi_slv_apb4),
  .PSTRB                (pstrb_qspi_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam qspi_slv_apb4.APB_TYPE = 4;
defparam qspi_slv_apb4.ID_WIDTH = 4;
defparam qspi_slv_apb4.INSTANCE = "qspi_slv_apb4";


apb4_s_if     rcu_slv_apb4 (
  .PADDR                (paddr_rcu_slv_apb4),
  .PWDATA               (pwdata_rcu_slv_apb4),
  .PWRITE               (pwrite_rcu_slv_apb4),
  .PENABLE              (penable_rcu_slv_apb4),
  .PSEL                 (pselx_rcu_slv_apb4),
  .PRDATA               (prdata_rcu_slv_apb4),
  .PSLVERR              (pslverr_rcu_slv_apb4),
  .PREADY               (pready_rcu_slv_apb4),
  .PPROT                (pprot_rcu_slv_apb4),
  .PSTRB                (pstrb_rcu_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam rcu_slv_apb4.APB_TYPE = 4;
defparam rcu_slv_apb4.ID_WIDTH = 4;
defparam rcu_slv_apb4.INSTANCE = "rcu_slv_apb4";


apb4_s_if     rng_slv_apb4 (
  .PADDR                (paddr_rng_slv_apb4),
  .PWDATA               (pwdata_rng_slv_apb4),
  .PWRITE               (pwrite_rng_slv_apb4),
  .PENABLE              (penable_rng_slv_apb4),
  .PSEL                 (pselx_rng_slv_apb4),
  .PRDATA               (prdata_rng_slv_apb4),
  .PSLVERR              (pslverr_rng_slv_apb4),
  .PREADY               (pready_rng_slv_apb4),
  .PPROT                (pprot_rng_slv_apb4),
  .PSTRB                (pstrb_rng_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam rng_slv_apb4.APB_TYPE = 4;
defparam rng_slv_apb4.ID_WIDTH = 4;
defparam rng_slv_apb4.INSTANCE = "rng_slv_apb4";


apb4_s_if     rtc_slv_apb4 (
  .PADDR                (paddr_rtc_slv_apb4),
  .PWDATA               (pwdata_rtc_slv_apb4),
  .PWRITE               (pwrite_rtc_slv_apb4),
  .PENABLE              (penable_rtc_slv_apb4),
  .PSEL                 (pselx_rtc_slv_apb4),
  .PRDATA               (prdata_rtc_slv_apb4),
  .PSLVERR              (pslverr_rtc_slv_apb4),
  .PREADY               (pready_rtc_slv_apb4),
  .PPROT                (pprot_rtc_slv_apb4),
  .PSTRB                (pstrb_rtc_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam rtc_slv_apb4.APB_TYPE = 4;
defparam rtc_slv_apb4.ID_WIDTH = 4;
defparam rtc_slv_apb4.INSTANCE = "rtc_slv_apb4";


axi4_s_if     sdram_slv_axi4 (
  .WAIT_REQ             (wait_req_sdram_slv_axi4_event),
  .WAIT_ACK             (wait_ack_sdram_slv_axi4_event),
  .WAIT_DATA            (wait_data_sdram_slv_axi4_event),
  .EMIT_REQ             (emit_req_sdram_slv_axi4_event),
  .EMIT_ACK             (emit_ack_sdram_slv_axi4_event),
  .EMIT_DATA            (emit_data_sdram_slv_axi4_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_sdram_slv_axi4_apb),
  .PRDATA               (prdata_sdram_slv_axi4_apb),
  .PSLVERR              (pslverr_sdram_slv_axi4_apb),
  .PREADY               (pready_sdram_slv_axi4_apb),
  .ACLK                 (clk_peri_100mclk),
  .ARESETn              (clk_peri_100mresetn),
  .AWID                 (awid_sdram_slv_axi4),
  .AWADDR               (awaddr_sdram_slv_axi4),
  .AWLEN                (awlen_sdram_slv_axi4),
  .AWQOS                (4'b0),
  .AWSIZE               (awsize_sdram_slv_axi4),
  .AWBURST              (awburst_sdram_slv_axi4),
  .AWLOCK               (awlock_sdram_slv_axi4),
  .AWCACHE              (awcache_sdram_slv_axi4),
  .AWPROT               (awprot_sdram_slv_axi4),
  .AWVALID              (awvalid_sdram_slv_axi4),
  .AWREGION             (4'b0),
  .AWREADY              (awready_sdram_slv_axi4),
  .WDATA                (wdata_sdram_slv_axi4),
  .WSTRB                (wstrb_sdram_slv_axi4),
  .WLAST                (wlast_sdram_slv_axi4),
  .WVALID               (wvalid_sdram_slv_axi4),
  .WREADY               (wready_sdram_slv_axi4),
  .BID                  (bid_sdram_slv_axi4),
  .BRESP                (bresp_sdram_slv_axi4),
  .BVALID               (bvalid_sdram_slv_axi4),
  .BREADY               (bready_sdram_slv_axi4),
  .ARID                 (arid_sdram_slv_axi4),
  .ARADDR               (araddr_sdram_slv_axi4),
  .ARLEN                (arlen_sdram_slv_axi4),
  .ARQOS                (4'b0),
  .ARSIZE               (arsize_sdram_slv_axi4),
  .ARBURST              (arburst_sdram_slv_axi4),
  .ARLOCK               (arlock_sdram_slv_axi4),
  .ARCACHE              (arcache_sdram_slv_axi4),
  .ARPROT               (arprot_sdram_slv_axi4),
  .ARVALID              (arvalid_sdram_slv_axi4),
  .ARREGION             (4'b0),
  .ARREADY              (arready_sdram_slv_axi4),
  .RID                  (rid_sdram_slv_axi4),
  .RDATA                (rdata_sdram_slv_axi4),
  .RRESP                (rresp_sdram_slv_axi4),
  .RLAST                (rlast_sdram_slv_axi4),
  .RVALID               (rvalid_sdram_slv_axi4),
  .RREADY               (rready_sdram_slv_axi4),
  .AWUSER               ({(sdram_slv_axi4_AWUSER_WIDTH-1 + 1){1'b0}}),
  .WUSER                ({(sdram_slv_axi4_WUSER_WIDTH-1 + 1){1'b0}}),
  .BUSER                (),
  .ARUSER               ({(sdram_slv_axi4_ARUSER_WIDTH-1 + 1){1'b0}}),
  .RUSER                (),
  .ACLKEN               (1'b0)
);
defparam sdram_slv_axi4.ADDR_WIDTH = 32;
defparam sdram_slv_axi4.ARUSER_WIDTH = sdram_slv_axi4_ARUSER_WIDTH;
defparam sdram_slv_axi4.AWUSER_WIDTH = sdram_slv_axi4_AWUSER_WIDTH;
defparam sdram_slv_axi4.BUSER_WIDTH = sdram_slv_axi4_BUSER_WIDTH;
defparam sdram_slv_axi4.DATA_WIDTH = 32;
defparam sdram_slv_axi4.DriveOnlyOnEnable = sdram_slv_axi4_DriveOnlyOnEnable;
defparam sdram_slv_axi4.EW_WIDTH = 16;
defparam sdram_slv_axi4.ID_WIDTH = 4;
defparam sdram_slv_axi4.INSTANCE = "sdram_slv_axi4";
defparam sdram_slv_axi4.PortIsInternal = sdram_slv_axi4_PortIsInternal;
defparam sdram_slv_axi4.RUSER_WIDTH = sdram_slv_axi4_RUSER_WIDTH;
defparam sdram_slv_axi4.STRB_WIDTH = 4;
defparam sdram_slv_axi4.USE_X = sdram_slv_axi4_USE_X;
defparam sdram_slv_axi4.VALID_WIDTH = 1;
defparam sdram_slv_axi4.WUSER_WIDTH = sdram_slv_axi4_WUSER_WIDTH;
defparam sdram_slv_axi4.combined_issuing_capability = sdram_slv_axi4_combined_issuing_capability;
defparam sdram_slv_axi4.leading_writes = sdram_slv_axi4_leading_writes;
defparam sdram_slv_axi4.limit_acceptance_capability = 1;
defparam sdram_slv_axi4.read_issuing_capability = 4;
defparam sdram_slv_axi4.regions_flag = 1;
defparam sdram_slv_axi4.write_issuing_capability = 4;


apb4_s_if     spfs_slv_apb4_tpv (
  .PADDR                (paddr_spfs_slv_apb4_tpv),
  .PWDATA               (pwdata_spfs_slv_apb4_tpv),
  .PWRITE               (pwrite_spfs_slv_apb4_tpv),
  .PENABLE              (penable_spfs_slv_apb4_tpv),
  .PSEL                 (pselx_spfs_slv_apb4_tpv),
  .PRDATA               (prdata_spfs_slv_apb4_tpv),
  .PSLVERR              (pslverr_spfs_slv_apb4_tpv),
  .PREADY               (pready_spfs_slv_apb4_tpv),
  .PPROT                (pprot_spfs_slv_apb4_tpv),
  .PSTRB                (pstrb_spfs_slv_apb4_tpv),
  .PCLK                 (clk_peri_25mclk),
  .PCLKEN               (clk_peri_25mclken),
  .presetn              (clk_peri_25mresetn)
);
defparam spfs_slv_apb4_tpv.APB_TYPE = 4;
defparam spfs_slv_apb4_tpv.ID_WIDTH = 4;
defparam spfs_slv_apb4_tpv.INSTANCE = "spfs_slv_apb4_tpv";


apb4_s_if     spi0_slv_apb4 (
  .PADDR                (paddr_spi0_slv_apb4),
  .PWDATA               (pwdata_spi0_slv_apb4),
  .PWRITE               (pwrite_spi0_slv_apb4),
  .PENABLE              (penable_spi0_slv_apb4),
  .PSEL                 (pselx_spi0_slv_apb4),
  .PRDATA               (prdata_spi0_slv_apb4),
  .PSLVERR              (pslverr_spi0_slv_apb4),
  .PREADY               (pready_spi0_slv_apb4),
  .PPROT                (pprot_spi0_slv_apb4),
  .PSTRB                (pstrb_spi0_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam spi0_slv_apb4.APB_TYPE = 4;
defparam spi0_slv_apb4.ID_WIDTH = 4;
defparam spi0_slv_apb4.INSTANCE = "spi0_slv_apb4";


apb4_s_if     spi1_slv_apb4 (
  .PADDR                (paddr_spi1_slv_apb4),
  .PWDATA               (pwdata_spi1_slv_apb4),
  .PWRITE               (pwrite_spi1_slv_apb4),
  .PENABLE              (penable_spi1_slv_apb4),
  .PSEL                 (pselx_spi1_slv_apb4),
  .PRDATA               (prdata_spi1_slv_apb4),
  .PSLVERR              (pslverr_spi1_slv_apb4),
  .PREADY               (pready_spi1_slv_apb4),
  .PPROT                (pprot_spi1_slv_apb4),
  .PSTRB                (pstrb_spi1_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam spi1_slv_apb4.APB_TYPE = 4;
defparam spi1_slv_apb4.ID_WIDTH = 4;
defparam spi1_slv_apb4.INSTANCE = "spi1_slv_apb4";


axi4_s_if     sram_slv_axi4 (
  .WAIT_REQ             (wait_req_sram_slv_axi4_event),
  .WAIT_ACK             (wait_ack_sram_slv_axi4_event),
  .WAIT_DATA            (wait_data_sram_slv_axi4_event),
  .EMIT_REQ             (emit_req_sram_slv_axi4_event),
  .EMIT_ACK             (emit_ack_sram_slv_axi4_event),
  .EMIT_DATA            (emit_data_sram_slv_axi4_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_sram_slv_axi4_apb),
  .PRDATA               (prdata_sram_slv_axi4_apb),
  .PSLVERR              (pslverr_sram_slv_axi4_apb),
  .PREADY               (pready_sram_slv_axi4_apb),
  .ACLK                 (clk_core_200_800mclk),
  .ARESETn              (clk_core_200_800mresetn),
  .AWID                 (awid_sram_slv_axi4),
  .AWADDR               (awaddr_sram_slv_axi4),
  .AWLEN                (awlen_sram_slv_axi4),
  .AWQOS                (4'b0),
  .AWSIZE               (awsize_sram_slv_axi4),
  .AWBURST              (awburst_sram_slv_axi4),
  .AWLOCK               (awlock_sram_slv_axi4),
  .AWCACHE              (awcache_sram_slv_axi4),
  .AWPROT               (awprot_sram_slv_axi4),
  .AWVALID              (awvalid_sram_slv_axi4),
  .AWREGION             (4'b0),
  .AWREADY              (awready_sram_slv_axi4),
  .WDATA                (wdata_sram_slv_axi4),
  .WSTRB                (wstrb_sram_slv_axi4),
  .WLAST                (wlast_sram_slv_axi4),
  .WVALID               (wvalid_sram_slv_axi4),
  .WREADY               (wready_sram_slv_axi4),
  .BID                  (bid_sram_slv_axi4),
  .BRESP                (bresp_sram_slv_axi4),
  .BVALID               (bvalid_sram_slv_axi4),
  .BREADY               (bready_sram_slv_axi4),
  .ARID                 (arid_sram_slv_axi4),
  .ARADDR               (araddr_sram_slv_axi4),
  .ARLEN                (arlen_sram_slv_axi4),
  .ARQOS                (4'b0),
  .ARSIZE               (arsize_sram_slv_axi4),
  .ARBURST              (arburst_sram_slv_axi4),
  .ARLOCK               (arlock_sram_slv_axi4),
  .ARCACHE              (arcache_sram_slv_axi4),
  .ARPROT               (arprot_sram_slv_axi4),
  .ARVALID              (arvalid_sram_slv_axi4),
  .ARREGION             (4'b0),
  .ARREADY              (arready_sram_slv_axi4),
  .RID                  (rid_sram_slv_axi4),
  .RDATA                (rdata_sram_slv_axi4),
  .RRESP                (rresp_sram_slv_axi4),
  .RLAST                (rlast_sram_slv_axi4),
  .RVALID               (rvalid_sram_slv_axi4),
  .RREADY               (rready_sram_slv_axi4),
  .AWUSER               ({(sram_slv_axi4_AWUSER_WIDTH-1 + 1){1'b0}}),
  .WUSER                ({(sram_slv_axi4_WUSER_WIDTH-1 + 1){1'b0}}),
  .BUSER                (),
  .ARUSER               ({(sram_slv_axi4_ARUSER_WIDTH-1 + 1){1'b0}}),
  .RUSER                (),
  .ACLKEN               (1'b0)
);
defparam sram_slv_axi4.ADDR_WIDTH = 32;
defparam sram_slv_axi4.ARUSER_WIDTH = sram_slv_axi4_ARUSER_WIDTH;
defparam sram_slv_axi4.AWUSER_WIDTH = sram_slv_axi4_AWUSER_WIDTH;
defparam sram_slv_axi4.BUSER_WIDTH = sram_slv_axi4_BUSER_WIDTH;
defparam sram_slv_axi4.DATA_WIDTH = 64;
defparam sram_slv_axi4.DriveOnlyOnEnable = sram_slv_axi4_DriveOnlyOnEnable;
defparam sram_slv_axi4.EW_WIDTH = 16;
defparam sram_slv_axi4.ID_WIDTH = 4;
defparam sram_slv_axi4.INSTANCE = "sram_slv_axi4";
defparam sram_slv_axi4.PortIsInternal = sram_slv_axi4_PortIsInternal;
defparam sram_slv_axi4.RUSER_WIDTH = sram_slv_axi4_RUSER_WIDTH;
defparam sram_slv_axi4.STRB_WIDTH = 8;
defparam sram_slv_axi4.USE_X = sram_slv_axi4_USE_X;
defparam sram_slv_axi4.VALID_WIDTH = 1;
defparam sram_slv_axi4.WUSER_WIDTH = sram_slv_axi4_WUSER_WIDTH;
defparam sram_slv_axi4.combined_issuing_capability = sram_slv_axi4_combined_issuing_capability;
defparam sram_slv_axi4.leading_writes = sram_slv_axi4_leading_writes;
defparam sram_slv_axi4.limit_acceptance_capability = 1;
defparam sram_slv_axi4.read_issuing_capability = 1;
defparam sram_slv_axi4.regions_flag = 1;
defparam sram_slv_axi4.write_issuing_capability = 1;


apb4_s_if     tim0_slv_apb4 (
  .PADDR                (paddr_tim0_slv_apb4),
  .PWDATA               (pwdata_tim0_slv_apb4),
  .PWRITE               (pwrite_tim0_slv_apb4),
  .PENABLE              (penable_tim0_slv_apb4),
  .PSEL                 (pselx_tim0_slv_apb4),
  .PRDATA               (prdata_tim0_slv_apb4),
  .PSLVERR              (pslverr_tim0_slv_apb4),
  .PREADY               (pready_tim0_slv_apb4),
  .PPROT                (pprot_tim0_slv_apb4),
  .PSTRB                (pstrb_tim0_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam tim0_slv_apb4.APB_TYPE = 4;
defparam tim0_slv_apb4.ID_WIDTH = 4;
defparam tim0_slv_apb4.INSTANCE = "tim0_slv_apb4";


apb4_s_if     tim1_slv_apb4 (
  .PADDR                (paddr_tim1_slv_apb4),
  .PWDATA               (pwdata_tim1_slv_apb4),
  .PWRITE               (pwrite_tim1_slv_apb4),
  .PENABLE              (penable_tim1_slv_apb4),
  .PSEL                 (pselx_tim1_slv_apb4),
  .PRDATA               (prdata_tim1_slv_apb4),
  .PSLVERR              (pslverr_tim1_slv_apb4),
  .PREADY               (pready_tim1_slv_apb4),
  .PPROT                (pprot_tim1_slv_apb4),
  .PSTRB                (pstrb_tim1_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam tim1_slv_apb4.APB_TYPE = 4;
defparam tim1_slv_apb4.ID_WIDTH = 4;
defparam tim1_slv_apb4.INSTANCE = "tim1_slv_apb4";


apb4_s_if     tim2_slv_apb4 (
  .PADDR                (paddr_tim2_slv_apb4),
  .PWDATA               (pwdata_tim2_slv_apb4),
  .PWRITE               (pwrite_tim2_slv_apb4),
  .PENABLE              (penable_tim2_slv_apb4),
  .PSEL                 (pselx_tim2_slv_apb4),
  .PRDATA               (prdata_tim2_slv_apb4),
  .PSLVERR              (pslverr_tim2_slv_apb4),
  .PREADY               (pready_tim2_slv_apb4),
  .PPROT                (pprot_tim2_slv_apb4),
  .PSTRB                (pstrb_tim2_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam tim2_slv_apb4.APB_TYPE = 4;
defparam tim2_slv_apb4.ID_WIDTH = 4;
defparam tim2_slv_apb4.INSTANCE = "tim2_slv_apb4";


apb4_s_if     tim3_slv_apb4 (
  .PADDR                (paddr_tim3_slv_apb4),
  .PWDATA               (pwdata_tim3_slv_apb4),
  .PWRITE               (pwrite_tim3_slv_apb4),
  .PENABLE              (penable_tim3_slv_apb4),
  .PSEL                 (pselx_tim3_slv_apb4),
  .PRDATA               (prdata_tim3_slv_apb4),
  .PSLVERR              (pslverr_tim3_slv_apb4),
  .PREADY               (pready_tim3_slv_apb4),
  .PPROT                (pprot_tim3_slv_apb4),
  .PSTRB                (pstrb_tim3_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam tim3_slv_apb4.APB_TYPE = 4;
defparam tim3_slv_apb4.ID_WIDTH = 4;
defparam tim3_slv_apb4.INSTANCE = "tim3_slv_apb4";


nic400_ysyx_rv32     u_nic400 (
  .paddr_archinfo_slv_apb4 (paddr_archinfo_slv_apb4),
  .pselx_archinfo_slv_apb4 (pselx_archinfo_slv_apb4),
  .penable_archinfo_slv_apb4 (penable_archinfo_slv_apb4),
  .pwrite_archinfo_slv_apb4 (pwrite_archinfo_slv_apb4),
  .prdata_archinfo_slv_apb4 (prdata_archinfo_slv_apb4),
  .pwdata_archinfo_slv_apb4 (pwdata_archinfo_slv_apb4),
  .pprot_archinfo_slv_apb4 (pprot_archinfo_slv_apb4),
  .pstrb_archinfo_slv_apb4 (pstrb_archinfo_slv_apb4),
  .pready_archinfo_slv_apb4 (pready_archinfo_slv_apb4),
  .pslverr_archinfo_slv_apb4 (pslverr_archinfo_slv_apb4),
  .awid_chiplink_slv_axi4_tpv (awid_chiplink_slv_axi4_tpv),
  .awaddr_chiplink_slv_axi4_tpv (awaddr_chiplink_slv_axi4_tpv),
  .awlen_chiplink_slv_axi4_tpv (awlen_chiplink_slv_axi4_tpv),
  .awsize_chiplink_slv_axi4_tpv (awsize_chiplink_slv_axi4_tpv),
  .awburst_chiplink_slv_axi4_tpv (awburst_chiplink_slv_axi4_tpv),
  .awlock_chiplink_slv_axi4_tpv (awlock_chiplink_slv_axi4_tpv),
  .awcache_chiplink_slv_axi4_tpv (awcache_chiplink_slv_axi4_tpv),
  .awprot_chiplink_slv_axi4_tpv (awprot_chiplink_slv_axi4_tpv),
  .awvalid_chiplink_slv_axi4_tpv (awvalid_chiplink_slv_axi4_tpv),
  .awready_chiplink_slv_axi4_tpv (awready_chiplink_slv_axi4_tpv),
  .wdata_chiplink_slv_axi4_tpv (wdata_chiplink_slv_axi4_tpv),
  .wstrb_chiplink_slv_axi4_tpv (wstrb_chiplink_slv_axi4_tpv),
  .wlast_chiplink_slv_axi4_tpv (wlast_chiplink_slv_axi4_tpv),
  .wvalid_chiplink_slv_axi4_tpv (wvalid_chiplink_slv_axi4_tpv),
  .wready_chiplink_slv_axi4_tpv (wready_chiplink_slv_axi4_tpv),
  .bid_chiplink_slv_axi4_tpv (bid_chiplink_slv_axi4_tpv),
  .bresp_chiplink_slv_axi4_tpv (bresp_chiplink_slv_axi4_tpv),
  .bvalid_chiplink_slv_axi4_tpv (bvalid_chiplink_slv_axi4_tpv),
  .bready_chiplink_slv_axi4_tpv (bready_chiplink_slv_axi4_tpv),
  .arid_chiplink_slv_axi4_tpv (arid_chiplink_slv_axi4_tpv),
  .araddr_chiplink_slv_axi4_tpv (araddr_chiplink_slv_axi4_tpv),
  .arlen_chiplink_slv_axi4_tpv (arlen_chiplink_slv_axi4_tpv),
  .arsize_chiplink_slv_axi4_tpv (arsize_chiplink_slv_axi4_tpv),
  .arburst_chiplink_slv_axi4_tpv (arburst_chiplink_slv_axi4_tpv),
  .arlock_chiplink_slv_axi4_tpv (arlock_chiplink_slv_axi4_tpv),
  .arcache_chiplink_slv_axi4_tpv (arcache_chiplink_slv_axi4_tpv),
  .arprot_chiplink_slv_axi4_tpv (arprot_chiplink_slv_axi4_tpv),
  .arvalid_chiplink_slv_axi4_tpv (arvalid_chiplink_slv_axi4_tpv),
  .arready_chiplink_slv_axi4_tpv (arready_chiplink_slv_axi4_tpv),
  .rid_chiplink_slv_axi4_tpv (rid_chiplink_slv_axi4_tpv),
  .rdata_chiplink_slv_axi4_tpv (rdata_chiplink_slv_axi4_tpv),
  .rresp_chiplink_slv_axi4_tpv (rresp_chiplink_slv_axi4_tpv),
  .rlast_chiplink_slv_axi4_tpv (rlast_chiplink_slv_axi4_tpv),
  .rvalid_chiplink_slv_axi4_tpv (rvalid_chiplink_slv_axi4_tpv),
  .rready_chiplink_slv_axi4_tpv (rready_chiplink_slv_axi4_tpv),
  .paddr_clint_slv_apb4 (paddr_clint_slv_apb4),
  .pselx_clint_slv_apb4 (pselx_clint_slv_apb4),
  .penable_clint_slv_apb4 (penable_clint_slv_apb4),
  .pwrite_clint_slv_apb4 (pwrite_clint_slv_apb4),
  .prdata_clint_slv_apb4 (prdata_clint_slv_apb4),
  .pwdata_clint_slv_apb4 (pwdata_clint_slv_apb4),
  .pprot_clint_slv_apb4 (pprot_clint_slv_apb4),
  .pstrb_clint_slv_apb4 (pstrb_clint_slv_apb4),
  .pready_clint_slv_apb4 (pready_clint_slv_apb4),
  .pslverr_clint_slv_apb4 (pslverr_clint_slv_apb4),
  .awid_cpu_mst_axi4    (awid_cpu_mst_axi4_data),
  .awaddr_cpu_mst_axi4  (awaddr_cpu_mst_axi4_data),
  .awlen_cpu_mst_axi4   (awlen_cpu_mst_axi4_data),
  .awsize_cpu_mst_axi4  (awsize_cpu_mst_axi4_data),
  .awburst_cpu_mst_axi4 (awburst_cpu_mst_axi4_data),
  .awlock_cpu_mst_axi4  (awlock_cpu_mst_axi4_data),
  .awcache_cpu_mst_axi4 (awcache_cpu_mst_axi4_data),
  .awprot_cpu_mst_axi4  (awprot_cpu_mst_axi4_data),
  .awvalid_cpu_mst_axi4 (awvalid_cpu_mst_axi4_data),
  .awready_cpu_mst_axi4 (awready_cpu_mst_axi4_data),
  .wdata_cpu_mst_axi4   (wdata_cpu_mst_axi4_data),
  .wstrb_cpu_mst_axi4   (wstrb_cpu_mst_axi4_data),
  .wlast_cpu_mst_axi4   (wlast_cpu_mst_axi4_data),
  .wvalid_cpu_mst_axi4  (wvalid_cpu_mst_axi4_data),
  .wready_cpu_mst_axi4  (wready_cpu_mst_axi4_data),
  .bid_cpu_mst_axi4     (bid_cpu_mst_axi4_data),
  .bresp_cpu_mst_axi4   (bresp_cpu_mst_axi4_data),
  .bvalid_cpu_mst_axi4  (bvalid_cpu_mst_axi4_data),
  .bready_cpu_mst_axi4  (bready_cpu_mst_axi4_data),
  .arid_cpu_mst_axi4    (arid_cpu_mst_axi4_data),
  .araddr_cpu_mst_axi4  (araddr_cpu_mst_axi4_data),
  .arlen_cpu_mst_axi4   (arlen_cpu_mst_axi4_data),
  .arsize_cpu_mst_axi4  (arsize_cpu_mst_axi4_data),
  .arburst_cpu_mst_axi4 (arburst_cpu_mst_axi4_data),
  .arlock_cpu_mst_axi4  (arlock_cpu_mst_axi4_data),
  .arcache_cpu_mst_axi4 (arcache_cpu_mst_axi4_data),
  .arprot_cpu_mst_axi4  (arprot_cpu_mst_axi4_data),
  .arvalid_cpu_mst_axi4 (arvalid_cpu_mst_axi4_data),
  .arready_cpu_mst_axi4 (arready_cpu_mst_axi4_data),
  .rid_cpu_mst_axi4     (rid_cpu_mst_axi4_data),
  .rdata_cpu_mst_axi4   (rdata_cpu_mst_axi4_data),
  .rresp_cpu_mst_axi4   (rresp_cpu_mst_axi4_data),
  .rlast_cpu_mst_axi4   (rlast_cpu_mst_axi4_data),
  .rvalid_cpu_mst_axi4  (rvalid_cpu_mst_axi4_data),
  .rready_cpu_mst_axi4  (rready_cpu_mst_axi4_data),
  .paddr_crc_slv_apb4   (paddr_crc_slv_apb4),
  .pselx_crc_slv_apb4   (pselx_crc_slv_apb4),
  .penable_crc_slv_apb4 (penable_crc_slv_apb4),
  .pwrite_crc_slv_apb4  (pwrite_crc_slv_apb4),
  .prdata_crc_slv_apb4  (prdata_crc_slv_apb4),
  .pwdata_crc_slv_apb4  (pwdata_crc_slv_apb4),
  .pprot_crc_slv_apb4   (pprot_crc_slv_apb4),
  .pstrb_crc_slv_apb4   (pstrb_crc_slv_apb4),
  .pready_crc_slv_apb4  (pready_crc_slv_apb4),
  .pslverr_crc_slv_apb4 (pslverr_crc_slv_apb4),
  .awid_dma_axi4_cpu_m  (awid_dma_axi4_cpu_m),
  .awaddr_dma_axi4_cpu_m (awaddr_dma_axi4_cpu_m),
  .awlen_dma_axi4_cpu_m (awlen_dma_axi4_cpu_m),
  .awsize_dma_axi4_cpu_m (awsize_dma_axi4_cpu_m),
  .awburst_dma_axi4_cpu_m (awburst_dma_axi4_cpu_m),
  .awlock_dma_axi4_cpu_m (awlock_dma_axi4_cpu_m),
  .awcache_dma_axi4_cpu_m (awcache_dma_axi4_cpu_m),
  .awprot_dma_axi4_cpu_m (awprot_dma_axi4_cpu_m),
  .awvalid_dma_axi4_cpu_m (awvalid_dma_axi4_cpu_m),
  .awready_dma_axi4_cpu_m (awready_dma_axi4_cpu_m),
  .wdata_dma_axi4_cpu_m (wdata_dma_axi4_cpu_m),
  .wstrb_dma_axi4_cpu_m (wstrb_dma_axi4_cpu_m),
  .wlast_dma_axi4_cpu_m (wlast_dma_axi4_cpu_m),
  .wvalid_dma_axi4_cpu_m (wvalid_dma_axi4_cpu_m),
  .wready_dma_axi4_cpu_m (wready_dma_axi4_cpu_m),
  .bid_dma_axi4_cpu_m   (bid_dma_axi4_cpu_m),
  .bresp_dma_axi4_cpu_m (bresp_dma_axi4_cpu_m),
  .bvalid_dma_axi4_cpu_m (bvalid_dma_axi4_cpu_m),
  .bready_dma_axi4_cpu_m (bready_dma_axi4_cpu_m),
  .arid_dma_axi4_cpu_m  (arid_dma_axi4_cpu_m),
  .araddr_dma_axi4_cpu_m (araddr_dma_axi4_cpu_m),
  .arlen_dma_axi4_cpu_m (arlen_dma_axi4_cpu_m),
  .arsize_dma_axi4_cpu_m (arsize_dma_axi4_cpu_m),
  .arburst_dma_axi4_cpu_m (arburst_dma_axi4_cpu_m),
  .arlock_dma_axi4_cpu_m (arlock_dma_axi4_cpu_m),
  .arcache_dma_axi4_cpu_m (arcache_dma_axi4_cpu_m),
  .arprot_dma_axi4_cpu_m (arprot_dma_axi4_cpu_m),
  .arvalid_dma_axi4_cpu_m (arvalid_dma_axi4_cpu_m),
  .arready_dma_axi4_cpu_m (arready_dma_axi4_cpu_m),
  .rid_dma_axi4_cpu_m   (rid_dma_axi4_cpu_m),
  .rdata_dma_axi4_cpu_m (rdata_dma_axi4_cpu_m),
  .rresp_dma_axi4_cpu_m (rresp_dma_axi4_cpu_m),
  .rlast_dma_axi4_cpu_m (rlast_dma_axi4_cpu_m),
  .rvalid_dma_axi4_cpu_m (rvalid_dma_axi4_cpu_m),
  .rready_dma_axi4_cpu_m (rready_dma_axi4_cpu_m),
  .awid_dma_axi4_cpu_s  (awid_dma_axi4_cpu_s_data),
  .awaddr_dma_axi4_cpu_s (awaddr_dma_axi4_cpu_s_data),
  .awlen_dma_axi4_cpu_s (awlen_dma_axi4_cpu_s_data),
  .awsize_dma_axi4_cpu_s (awsize_dma_axi4_cpu_s_data),
  .awburst_dma_axi4_cpu_s (awburst_dma_axi4_cpu_s_data),
  .awlock_dma_axi4_cpu_s (awlock_dma_axi4_cpu_s_data),
  .awcache_dma_axi4_cpu_s (awcache_dma_axi4_cpu_s_data),
  .awprot_dma_axi4_cpu_s (awprot_dma_axi4_cpu_s_data),
  .awvalid_dma_axi4_cpu_s (awvalid_dma_axi4_cpu_s_data),
  .awready_dma_axi4_cpu_s (awready_dma_axi4_cpu_s_data),
  .wdata_dma_axi4_cpu_s (wdata_dma_axi4_cpu_s_data),
  .wstrb_dma_axi4_cpu_s (wstrb_dma_axi4_cpu_s_data),
  .wlast_dma_axi4_cpu_s (wlast_dma_axi4_cpu_s_data),
  .wvalid_dma_axi4_cpu_s (wvalid_dma_axi4_cpu_s_data),
  .wready_dma_axi4_cpu_s (wready_dma_axi4_cpu_s_data),
  .bid_dma_axi4_cpu_s   (bid_dma_axi4_cpu_s_data),
  .bresp_dma_axi4_cpu_s (bresp_dma_axi4_cpu_s_data),
  .bvalid_dma_axi4_cpu_s (bvalid_dma_axi4_cpu_s_data),
  .bready_dma_axi4_cpu_s (bready_dma_axi4_cpu_s_data),
  .arid_dma_axi4_cpu_s  (arid_dma_axi4_cpu_s_data),
  .araddr_dma_axi4_cpu_s (araddr_dma_axi4_cpu_s_data),
  .arlen_dma_axi4_cpu_s (arlen_dma_axi4_cpu_s_data),
  .arsize_dma_axi4_cpu_s (arsize_dma_axi4_cpu_s_data),
  .arburst_dma_axi4_cpu_s (arburst_dma_axi4_cpu_s_data),
  .arlock_dma_axi4_cpu_s (arlock_dma_axi4_cpu_s_data),
  .arcache_dma_axi4_cpu_s (arcache_dma_axi4_cpu_s_data),
  .arprot_dma_axi4_cpu_s (arprot_dma_axi4_cpu_s_data),
  .arvalid_dma_axi4_cpu_s (arvalid_dma_axi4_cpu_s_data),
  .arready_dma_axi4_cpu_s (arready_dma_axi4_cpu_s_data),
  .rid_dma_axi4_cpu_s   (rid_dma_axi4_cpu_s_data),
  .rdata_dma_axi4_cpu_s (rdata_dma_axi4_cpu_s_data),
  .rresp_dma_axi4_cpu_s (rresp_dma_axi4_cpu_s_data),
  .rlast_dma_axi4_cpu_s (rlast_dma_axi4_cpu_s_data),
  .rvalid_dma_axi4_cpu_s (rvalid_dma_axi4_cpu_s_data),
  .rready_dma_axi4_cpu_s (rready_dma_axi4_cpu_s_data),
  .paddr_gpio_slv_apb4  (paddr_gpio_slv_apb4),
  .pselx_gpio_slv_apb4  (pselx_gpio_slv_apb4),
  .penable_gpio_slv_apb4 (penable_gpio_slv_apb4),
  .pwrite_gpio_slv_apb4 (pwrite_gpio_slv_apb4),
  .prdata_gpio_slv_apb4 (prdata_gpio_slv_apb4),
  .pwdata_gpio_slv_apb4 (pwdata_gpio_slv_apb4),
  .pprot_gpio_slv_apb4  (pprot_gpio_slv_apb4),
  .pstrb_gpio_slv_apb4  (pstrb_gpio_slv_apb4),
  .pready_gpio_slv_apb4 (pready_gpio_slv_apb4),
  .pslverr_gpio_slv_apb4 (pslverr_gpio_slv_apb4),
  .paddr_i2c_slv_apb4   (paddr_i2c_slv_apb4),
  .pselx_i2c_slv_apb4   (pselx_i2c_slv_apb4),
  .penable_i2c_slv_apb4 (penable_i2c_slv_apb4),
  .pwrite_i2c_slv_apb4  (pwrite_i2c_slv_apb4),
  .prdata_i2c_slv_apb4  (prdata_i2c_slv_apb4),
  .pwdata_i2c_slv_apb4  (pwdata_i2c_slv_apb4),
  .pprot_i2c_slv_apb4   (pprot_i2c_slv_apb4),
  .pstrb_i2c_slv_apb4   (pstrb_i2c_slv_apb4),
  .pready_i2c_slv_apb4  (pready_i2c_slv_apb4),
  .pslverr_i2c_slv_apb4 (pslverr_i2c_slv_apb4),
  .clk_aud_12288kclk    (clk_aud_12288kclk),
  .clk_aud_12288kresetn (clk_aud_12288kresetn),
  .paddr_i2s_slv_apb4   (paddr_i2s_slv_apb4),
  .pselx_i2s_slv_apb4   (pselx_i2s_slv_apb4),
  .penable_i2s_slv_apb4 (penable_i2s_slv_apb4),
  .pwrite_i2s_slv_apb4  (pwrite_i2s_slv_apb4),
  .prdata_i2s_slv_apb4  (prdata_i2s_slv_apb4),
  .pwdata_i2s_slv_apb4  (pwdata_i2s_slv_apb4),
  .pprot_i2s_slv_apb4   (pprot_i2s_slv_apb4),
  .pstrb_i2s_slv_apb4   (pstrb_i2s_slv_apb4),
  .pready_i2s_slv_apb4  (pready_i2s_slv_apb4),
  .pslverr_i2s_slv_apb4 (pslverr_i2s_slv_apb4),
  .clk_aud_12288kclken  (clk_aud_12288kclken),
  .paddr_plic_slv_apb4  (paddr_plic_slv_apb4),
  .pselx_plic_slv_apb4  (pselx_plic_slv_apb4),
  .penable_plic_slv_apb4 (penable_plic_slv_apb4),
  .pwrite_plic_slv_apb4 (pwrite_plic_slv_apb4),
  .prdata_plic_slv_apb4 (prdata_plic_slv_apb4),
  .pwdata_plic_slv_apb4 (pwdata_plic_slv_apb4),
  .pprot_plic_slv_apb4  (pprot_plic_slv_apb4),
  .pstrb_plic_slv_apb4  (pstrb_plic_slv_apb4),
  .pready_plic_slv_apb4 (pready_plic_slv_apb4),
  .pslverr_plic_slv_apb4 (pslverr_plic_slv_apb4),
  .paddr_ps2_slv_apb4   (paddr_ps2_slv_apb4),
  .pselx_ps2_slv_apb4   (pselx_ps2_slv_apb4),
  .penable_ps2_slv_apb4 (penable_ps2_slv_apb4),
  .pwrite_ps2_slv_apb4  (pwrite_ps2_slv_apb4),
  .prdata_ps2_slv_apb4  (prdata_ps2_slv_apb4),
  .pwdata_ps2_slv_apb4  (pwdata_ps2_slv_apb4),
  .pprot_ps2_slv_apb4   (pprot_ps2_slv_apb4),
  .pstrb_ps2_slv_apb4   (pstrb_ps2_slv_apb4),
  .pready_ps2_slv_apb4  (pready_ps2_slv_apb4),
  .pslverr_ps2_slv_apb4 (pslverr_ps2_slv_apb4),
  .paddr_psram_slv_apb4 (paddr_psram_slv_apb4),
  .pselx_psram_slv_apb4 (pselx_psram_slv_apb4),
  .penable_psram_slv_apb4 (penable_psram_slv_apb4),
  .pwrite_psram_slv_apb4 (pwrite_psram_slv_apb4),
  .prdata_psram_slv_apb4 (prdata_psram_slv_apb4),
  .pwdata_psram_slv_apb4 (pwdata_psram_slv_apb4),
  .pprot_psram_slv_apb4 (pprot_psram_slv_apb4),
  .pstrb_psram_slv_apb4 (pstrb_psram_slv_apb4),
  .pready_psram_slv_apb4 (pready_psram_slv_apb4),
  .pslverr_psram_slv_apb4 (pslverr_psram_slv_apb4),
  .awid_psram_slv_axi4  (awid_psram_slv_axi4),
  .awaddr_psram_slv_axi4 (awaddr_psram_slv_axi4),
  .awlen_psram_slv_axi4 (awlen_psram_slv_axi4),
  .awsize_psram_slv_axi4 (awsize_psram_slv_axi4),
  .awburst_psram_slv_axi4 (awburst_psram_slv_axi4),
  .awlock_psram_slv_axi4 (awlock_psram_slv_axi4),
  .awcache_psram_slv_axi4 (awcache_psram_slv_axi4),
  .awprot_psram_slv_axi4 (awprot_psram_slv_axi4),
  .awvalid_psram_slv_axi4 (awvalid_psram_slv_axi4),
  .awready_psram_slv_axi4 (awready_psram_slv_axi4),
  .wdata_psram_slv_axi4 (wdata_psram_slv_axi4),
  .wstrb_psram_slv_axi4 (wstrb_psram_slv_axi4),
  .wlast_psram_slv_axi4 (wlast_psram_slv_axi4),
  .wvalid_psram_slv_axi4 (wvalid_psram_slv_axi4),
  .wready_psram_slv_axi4 (wready_psram_slv_axi4),
  .bid_psram_slv_axi4   (bid_psram_slv_axi4),
  .bresp_psram_slv_axi4 (bresp_psram_slv_axi4),
  .bvalid_psram_slv_axi4 (bvalid_psram_slv_axi4),
  .bready_psram_slv_axi4 (bready_psram_slv_axi4),
  .arid_psram_slv_axi4  (arid_psram_slv_axi4),
  .araddr_psram_slv_axi4 (araddr_psram_slv_axi4),
  .arlen_psram_slv_axi4 (arlen_psram_slv_axi4),
  .arsize_psram_slv_axi4 (arsize_psram_slv_axi4),
  .arburst_psram_slv_axi4 (arburst_psram_slv_axi4),
  .arlock_psram_slv_axi4 (arlock_psram_slv_axi4),
  .arcache_psram_slv_axi4 (arcache_psram_slv_axi4),
  .arprot_psram_slv_axi4 (arprot_psram_slv_axi4),
  .arvalid_psram_slv_axi4 (arvalid_psram_slv_axi4),
  .arready_psram_slv_axi4 (arready_psram_slv_axi4),
  .rid_psram_slv_axi4   (rid_psram_slv_axi4),
  .rdata_psram_slv_axi4 (rdata_psram_slv_axi4),
  .rresp_psram_slv_axi4 (rresp_psram_slv_axi4),
  .rlast_psram_slv_axi4 (rlast_psram_slv_axi4),
  .rvalid_psram_slv_axi4 (rvalid_psram_slv_axi4),
  .rready_psram_slv_axi4 (rready_psram_slv_axi4),
  .paddr_pwm0_slv_apb4  (paddr_pwm0_slv_apb4),
  .pselx_pwm0_slv_apb4  (pselx_pwm0_slv_apb4),
  .penable_pwm0_slv_apb4 (penable_pwm0_slv_apb4),
  .pwrite_pwm0_slv_apb4 (pwrite_pwm0_slv_apb4),
  .prdata_pwm0_slv_apb4 (prdata_pwm0_slv_apb4),
  .pwdata_pwm0_slv_apb4 (pwdata_pwm0_slv_apb4),
  .pprot_pwm0_slv_apb4  (pprot_pwm0_slv_apb4),
  .pstrb_pwm0_slv_apb4  (pstrb_pwm0_slv_apb4),
  .pready_pwm0_slv_apb4 (pready_pwm0_slv_apb4),
  .pslverr_pwm0_slv_apb4 (pslverr_pwm0_slv_apb4),
  .paddr_pwm1_slv_apb4  (paddr_pwm1_slv_apb4),
  .pselx_pwm1_slv_apb4  (pselx_pwm1_slv_apb4),
  .penable_pwm1_slv_apb4 (penable_pwm1_slv_apb4),
  .pwrite_pwm1_slv_apb4 (pwrite_pwm1_slv_apb4),
  .prdata_pwm1_slv_apb4 (prdata_pwm1_slv_apb4),
  .pwdata_pwm1_slv_apb4 (pwdata_pwm1_slv_apb4),
  .pprot_pwm1_slv_apb4  (pprot_pwm1_slv_apb4),
  .pstrb_pwm1_slv_apb4  (pstrb_pwm1_slv_apb4),
  .pready_pwm1_slv_apb4 (pready_pwm1_slv_apb4),
  .pslverr_pwm1_slv_apb4 (pslverr_pwm1_slv_apb4),
  .paddr_pwm2_slv_apb4  (paddr_pwm2_slv_apb4),
  .pselx_pwm2_slv_apb4  (pselx_pwm2_slv_apb4),
  .penable_pwm2_slv_apb4 (penable_pwm2_slv_apb4),
  .pwrite_pwm2_slv_apb4 (pwrite_pwm2_slv_apb4),
  .prdata_pwm2_slv_apb4 (prdata_pwm2_slv_apb4),
  .pwdata_pwm2_slv_apb4 (pwdata_pwm2_slv_apb4),
  .pprot_pwm2_slv_apb4  (pprot_pwm2_slv_apb4),
  .pstrb_pwm2_slv_apb4  (pstrb_pwm2_slv_apb4),
  .pready_pwm2_slv_apb4 (pready_pwm2_slv_apb4),
  .pslverr_pwm2_slv_apb4 (pslverr_pwm2_slv_apb4),
  .paddr_qspi_slv_apb4  (paddr_qspi_slv_apb4),
  .pselx_qspi_slv_apb4  (pselx_qspi_slv_apb4),
  .penable_qspi_slv_apb4 (penable_qspi_slv_apb4),
  .pwrite_qspi_slv_apb4 (pwrite_qspi_slv_apb4),
  .prdata_qspi_slv_apb4 (prdata_qspi_slv_apb4),
  .pwdata_qspi_slv_apb4 (pwdata_qspi_slv_apb4),
  .pprot_qspi_slv_apb4  (pprot_qspi_slv_apb4),
  .pstrb_qspi_slv_apb4  (pstrb_qspi_slv_apb4),
  .pready_qspi_slv_apb4 (pready_qspi_slv_apb4),
  .pslverr_qspi_slv_apb4 (pslverr_qspi_slv_apb4),
  .paddr_rcu_slv_apb4   (paddr_rcu_slv_apb4),
  .pselx_rcu_slv_apb4   (pselx_rcu_slv_apb4),
  .penable_rcu_slv_apb4 (penable_rcu_slv_apb4),
  .pwrite_rcu_slv_apb4  (pwrite_rcu_slv_apb4),
  .prdata_rcu_slv_apb4  (prdata_rcu_slv_apb4),
  .pwdata_rcu_slv_apb4  (pwdata_rcu_slv_apb4),
  .pprot_rcu_slv_apb4   (pprot_rcu_slv_apb4),
  .pstrb_rcu_slv_apb4   (pstrb_rcu_slv_apb4),
  .pready_rcu_slv_apb4  (pready_rcu_slv_apb4),
  .pslverr_rcu_slv_apb4 (pslverr_rcu_slv_apb4),
  .paddr_rng_slv_apb4   (paddr_rng_slv_apb4),
  .pselx_rng_slv_apb4   (pselx_rng_slv_apb4),
  .penable_rng_slv_apb4 (penable_rng_slv_apb4),
  .pwrite_rng_slv_apb4  (pwrite_rng_slv_apb4),
  .prdata_rng_slv_apb4  (prdata_rng_slv_apb4),
  .pwdata_rng_slv_apb4  (pwdata_rng_slv_apb4),
  .pprot_rng_slv_apb4   (pprot_rng_slv_apb4),
  .pstrb_rng_slv_apb4   (pstrb_rng_slv_apb4),
  .pready_rng_slv_apb4  (pready_rng_slv_apb4),
  .pslverr_rng_slv_apb4 (pslverr_rng_slv_apb4),
  .paddr_rtc_slv_apb4   (paddr_rtc_slv_apb4),
  .pselx_rtc_slv_apb4   (pselx_rtc_slv_apb4),
  .penable_rtc_slv_apb4 (penable_rtc_slv_apb4),
  .pwrite_rtc_slv_apb4  (pwrite_rtc_slv_apb4),
  .prdata_rtc_slv_apb4  (prdata_rtc_slv_apb4),
  .pwdata_rtc_slv_apb4  (pwdata_rtc_slv_apb4),
  .pprot_rtc_slv_apb4   (pprot_rtc_slv_apb4),
  .pstrb_rtc_slv_apb4   (pstrb_rtc_slv_apb4),
  .pready_rtc_slv_apb4  (pready_rtc_slv_apb4),
  .pslverr_rtc_slv_apb4 (pslverr_rtc_slv_apb4),
  .awid_sdram_slv_axi4  (awid_sdram_slv_axi4),
  .awaddr_sdram_slv_axi4 (awaddr_sdram_slv_axi4),
  .awlen_sdram_slv_axi4 (awlen_sdram_slv_axi4),
  .awsize_sdram_slv_axi4 (awsize_sdram_slv_axi4),
  .awburst_sdram_slv_axi4 (awburst_sdram_slv_axi4),
  .awlock_sdram_slv_axi4 (awlock_sdram_slv_axi4),
  .awcache_sdram_slv_axi4 (awcache_sdram_slv_axi4),
  .awprot_sdram_slv_axi4 (awprot_sdram_slv_axi4),
  .awvalid_sdram_slv_axi4 (awvalid_sdram_slv_axi4),
  .awready_sdram_slv_axi4 (awready_sdram_slv_axi4),
  .wdata_sdram_slv_axi4 (wdata_sdram_slv_axi4),
  .wstrb_sdram_slv_axi4 (wstrb_sdram_slv_axi4),
  .wlast_sdram_slv_axi4 (wlast_sdram_slv_axi4),
  .wvalid_sdram_slv_axi4 (wvalid_sdram_slv_axi4),
  .wready_sdram_slv_axi4 (wready_sdram_slv_axi4),
  .bid_sdram_slv_axi4   (bid_sdram_slv_axi4),
  .bresp_sdram_slv_axi4 (bresp_sdram_slv_axi4),
  .bvalid_sdram_slv_axi4 (bvalid_sdram_slv_axi4),
  .bready_sdram_slv_axi4 (bready_sdram_slv_axi4),
  .arid_sdram_slv_axi4  (arid_sdram_slv_axi4),
  .araddr_sdram_slv_axi4 (araddr_sdram_slv_axi4),
  .arlen_sdram_slv_axi4 (arlen_sdram_slv_axi4),
  .arsize_sdram_slv_axi4 (arsize_sdram_slv_axi4),
  .arburst_sdram_slv_axi4 (arburst_sdram_slv_axi4),
  .arlock_sdram_slv_axi4 (arlock_sdram_slv_axi4),
  .arcache_sdram_slv_axi4 (arcache_sdram_slv_axi4),
  .arprot_sdram_slv_axi4 (arprot_sdram_slv_axi4),
  .arvalid_sdram_slv_axi4 (arvalid_sdram_slv_axi4),
  .arready_sdram_slv_axi4 (arready_sdram_slv_axi4),
  .rid_sdram_slv_axi4   (rid_sdram_slv_axi4),
  .rdata_sdram_slv_axi4 (rdata_sdram_slv_axi4),
  .rresp_sdram_slv_axi4 (rresp_sdram_slv_axi4),
  .rlast_sdram_slv_axi4 (rlast_sdram_slv_axi4),
  .rvalid_sdram_slv_axi4 (rvalid_sdram_slv_axi4),
  .rready_sdram_slv_axi4 (rready_sdram_slv_axi4),
  .paddr_spfs_slv_apb4_tpv (paddr_spfs_slv_apb4_tpv),
  .pselx_spfs_slv_apb4_tpv (pselx_spfs_slv_apb4_tpv),
  .penable_spfs_slv_apb4_tpv (penable_spfs_slv_apb4_tpv),
  .pwrite_spfs_slv_apb4_tpv (pwrite_spfs_slv_apb4_tpv),
  .prdata_spfs_slv_apb4_tpv (prdata_spfs_slv_apb4_tpv),
  .pwdata_spfs_slv_apb4_tpv (pwdata_spfs_slv_apb4_tpv),
  .pprot_spfs_slv_apb4_tpv (pprot_spfs_slv_apb4_tpv),
  .pstrb_spfs_slv_apb4_tpv (pstrb_spfs_slv_apb4_tpv),
  .pready_spfs_slv_apb4_tpv (pready_spfs_slv_apb4_tpv),
  .pslverr_spfs_slv_apb4_tpv (pslverr_spfs_slv_apb4_tpv),
  .paddr_spi0_slv_apb4  (paddr_spi0_slv_apb4),
  .pselx_spi0_slv_apb4  (pselx_spi0_slv_apb4),
  .penable_spi0_slv_apb4 (penable_spi0_slv_apb4),
  .pwrite_spi0_slv_apb4 (pwrite_spi0_slv_apb4),
  .prdata_spi0_slv_apb4 (prdata_spi0_slv_apb4),
  .pwdata_spi0_slv_apb4 (pwdata_spi0_slv_apb4),
  .pprot_spi0_slv_apb4  (pprot_spi0_slv_apb4),
  .pstrb_spi0_slv_apb4  (pstrb_spi0_slv_apb4),
  .pready_spi0_slv_apb4 (pready_spi0_slv_apb4),
  .pslverr_spi0_slv_apb4 (pslverr_spi0_slv_apb4),
  .paddr_spi1_slv_apb4  (paddr_spi1_slv_apb4),
  .pselx_spi1_slv_apb4  (pselx_spi1_slv_apb4),
  .penable_spi1_slv_apb4 (penable_spi1_slv_apb4),
  .pwrite_spi1_slv_apb4 (pwrite_spi1_slv_apb4),
  .prdata_spi1_slv_apb4 (prdata_spi1_slv_apb4),
  .pwdata_spi1_slv_apb4 (pwdata_spi1_slv_apb4),
  .pprot_spi1_slv_apb4  (pprot_spi1_slv_apb4),
  .pstrb_spi1_slv_apb4  (pstrb_spi1_slv_apb4),
  .pready_spi1_slv_apb4 (pready_spi1_slv_apb4),
  .pslverr_spi1_slv_apb4 (pslverr_spi1_slv_apb4),
  .clk_core_200_800mclk (clk_core_200_800mclk),
  .clk_core_200_800mresetn (clk_core_200_800mresetn),
  .awid_sram_slv_axi4   (awid_sram_slv_axi4),
  .awaddr_sram_slv_axi4 (awaddr_sram_slv_axi4),
  .awlen_sram_slv_axi4  (awlen_sram_slv_axi4),
  .awsize_sram_slv_axi4 (awsize_sram_slv_axi4),
  .awburst_sram_slv_axi4 (awburst_sram_slv_axi4),
  .awlock_sram_slv_axi4 (awlock_sram_slv_axi4),
  .awcache_sram_slv_axi4 (awcache_sram_slv_axi4),
  .awprot_sram_slv_axi4 (awprot_sram_slv_axi4),
  .awvalid_sram_slv_axi4 (awvalid_sram_slv_axi4),
  .awready_sram_slv_axi4 (awready_sram_slv_axi4),
  .wdata_sram_slv_axi4  (wdata_sram_slv_axi4),
  .wstrb_sram_slv_axi4  (wstrb_sram_slv_axi4),
  .wlast_sram_slv_axi4  (wlast_sram_slv_axi4),
  .wvalid_sram_slv_axi4 (wvalid_sram_slv_axi4),
  .wready_sram_slv_axi4 (wready_sram_slv_axi4),
  .bid_sram_slv_axi4    (bid_sram_slv_axi4),
  .bresp_sram_slv_axi4  (bresp_sram_slv_axi4),
  .bvalid_sram_slv_axi4 (bvalid_sram_slv_axi4),
  .bready_sram_slv_axi4 (bready_sram_slv_axi4),
  .arid_sram_slv_axi4   (arid_sram_slv_axi4),
  .araddr_sram_slv_axi4 (araddr_sram_slv_axi4),
  .arlen_sram_slv_axi4  (arlen_sram_slv_axi4),
  .arsize_sram_slv_axi4 (arsize_sram_slv_axi4),
  .arburst_sram_slv_axi4 (arburst_sram_slv_axi4),
  .arlock_sram_slv_axi4 (arlock_sram_slv_axi4),
  .arcache_sram_slv_axi4 (arcache_sram_slv_axi4),
  .arprot_sram_slv_axi4 (arprot_sram_slv_axi4),
  .arvalid_sram_slv_axi4 (arvalid_sram_slv_axi4),
  .arready_sram_slv_axi4 (arready_sram_slv_axi4),
  .rid_sram_slv_axi4    (rid_sram_slv_axi4),
  .rdata_sram_slv_axi4  (rdata_sram_slv_axi4),
  .rresp_sram_slv_axi4  (rresp_sram_slv_axi4),
  .rlast_sram_slv_axi4  (rlast_sram_slv_axi4),
  .rvalid_sram_slv_axi4 (rvalid_sram_slv_axi4),
  .rready_sram_slv_axi4 (rready_sram_slv_axi4),
  .paddr_tim0_slv_apb4  (paddr_tim0_slv_apb4),
  .pselx_tim0_slv_apb4  (pselx_tim0_slv_apb4),
  .penable_tim0_slv_apb4 (penable_tim0_slv_apb4),
  .pwrite_tim0_slv_apb4 (pwrite_tim0_slv_apb4),
  .prdata_tim0_slv_apb4 (prdata_tim0_slv_apb4),
  .pwdata_tim0_slv_apb4 (pwdata_tim0_slv_apb4),
  .pprot_tim0_slv_apb4  (pprot_tim0_slv_apb4),
  .pstrb_tim0_slv_apb4  (pstrb_tim0_slv_apb4),
  .pready_tim0_slv_apb4 (pready_tim0_slv_apb4),
  .pslverr_tim0_slv_apb4 (pslverr_tim0_slv_apb4),
  .paddr_tim1_slv_apb4  (paddr_tim1_slv_apb4),
  .pselx_tim1_slv_apb4  (pselx_tim1_slv_apb4),
  .penable_tim1_slv_apb4 (penable_tim1_slv_apb4),
  .pwrite_tim1_slv_apb4 (pwrite_tim1_slv_apb4),
  .prdata_tim1_slv_apb4 (prdata_tim1_slv_apb4),
  .pwdata_tim1_slv_apb4 (pwdata_tim1_slv_apb4),
  .pprot_tim1_slv_apb4  (pprot_tim1_slv_apb4),
  .pstrb_tim1_slv_apb4  (pstrb_tim1_slv_apb4),
  .pready_tim1_slv_apb4 (pready_tim1_slv_apb4),
  .pslverr_tim1_slv_apb4 (pslverr_tim1_slv_apb4),
  .paddr_tim2_slv_apb4  (paddr_tim2_slv_apb4),
  .pselx_tim2_slv_apb4  (pselx_tim2_slv_apb4),
  .penable_tim2_slv_apb4 (penable_tim2_slv_apb4),
  .pwrite_tim2_slv_apb4 (pwrite_tim2_slv_apb4),
  .prdata_tim2_slv_apb4 (prdata_tim2_slv_apb4),
  .pwdata_tim2_slv_apb4 (pwdata_tim2_slv_apb4),
  .pprot_tim2_slv_apb4  (pprot_tim2_slv_apb4),
  .pstrb_tim2_slv_apb4  (pstrb_tim2_slv_apb4),
  .pready_tim2_slv_apb4 (pready_tim2_slv_apb4),
  .pslverr_tim2_slv_apb4 (pslverr_tim2_slv_apb4),
  .paddr_tim3_slv_apb4  (paddr_tim3_slv_apb4),
  .pselx_tim3_slv_apb4  (pselx_tim3_slv_apb4),
  .penable_tim3_slv_apb4 (penable_tim3_slv_apb4),
  .pwrite_tim3_slv_apb4 (pwrite_tim3_slv_apb4),
  .prdata_tim3_slv_apb4 (prdata_tim3_slv_apb4),
  .pwdata_tim3_slv_apb4 (pwdata_tim3_slv_apb4),
  .pprot_tim3_slv_apb4  (pprot_tim3_slv_apb4),
  .pstrb_tim3_slv_apb4  (pstrb_tim3_slv_apb4),
  .pready_tim3_slv_apb4 (pready_tim3_slv_apb4),
  .pslverr_tim3_slv_apb4 (pslverr_tim3_slv_apb4),
  .paddr_uart_slv_apb4  (paddr_uart_slv_apb4),
  .pselx_uart_slv_apb4  (pselx_uart_slv_apb4),
  .penable_uart_slv_apb4 (penable_uart_slv_apb4),
  .pwrite_uart_slv_apb4 (pwrite_uart_slv_apb4),
  .prdata_uart_slv_apb4 (prdata_uart_slv_apb4),
  .pwdata_uart_slv_apb4 (pwdata_uart_slv_apb4),
  .pprot_uart_slv_apb4  (pprot_uart_slv_apb4),
  .pstrb_uart_slv_apb4  (pstrb_uart_slv_apb4),
  .pready_uart_slv_apb4 (pready_uart_slv_apb4),
  .pslverr_uart_slv_apb4 (pslverr_uart_slv_apb4),
  .clk_peri_25mclk      (clk_peri_25mclk),
  .clk_peri_25mresetn   (clk_peri_25mresetn),
  .paddr_uart_slv_apb4_tpv (paddr_uart_slv_apb4_tpv),
  .pselx_uart_slv_apb4_tpv (pselx_uart_slv_apb4_tpv),
  .penable_uart_slv_apb4_tpv (penable_uart_slv_apb4_tpv),
  .pwrite_uart_slv_apb4_tpv (pwrite_uart_slv_apb4_tpv),
  .prdata_uart_slv_apb4_tpv (prdata_uart_slv_apb4_tpv),
  .pwdata_uart_slv_apb4_tpv (pwdata_uart_slv_apb4_tpv),
  .pprot_uart_slv_apb4_tpv (pprot_uart_slv_apb4_tpv),
  .pstrb_uart_slv_apb4_tpv (pstrb_uart_slv_apb4_tpv),
  .pready_uart_slv_apb4_tpv (pready_uart_slv_apb4_tpv),
  .pslverr_uart_slv_apb4_tpv (pslverr_uart_slv_apb4_tpv),
  .clk_peri_25mclken    (clk_peri_25mclken),
  .awid_vgalcd_mst_axi4 (awid_vgalcd_mst_axi4_data),
  .awaddr_vgalcd_mst_axi4 (awaddr_vgalcd_mst_axi4_data),
  .awlen_vgalcd_mst_axi4 (awlen_vgalcd_mst_axi4_data),
  .awsize_vgalcd_mst_axi4 (awsize_vgalcd_mst_axi4_data),
  .awburst_vgalcd_mst_axi4 (awburst_vgalcd_mst_axi4_data),
  .awlock_vgalcd_mst_axi4 (awlock_vgalcd_mst_axi4_data),
  .awcache_vgalcd_mst_axi4 (awcache_vgalcd_mst_axi4_data),
  .awprot_vgalcd_mst_axi4 (awprot_vgalcd_mst_axi4_data),
  .awvalid_vgalcd_mst_axi4 (awvalid_vgalcd_mst_axi4_data),
  .awready_vgalcd_mst_axi4 (awready_vgalcd_mst_axi4_data),
  .wdata_vgalcd_mst_axi4 (wdata_vgalcd_mst_axi4_data),
  .wstrb_vgalcd_mst_axi4 (wstrb_vgalcd_mst_axi4_data),
  .wlast_vgalcd_mst_axi4 (wlast_vgalcd_mst_axi4_data),
  .wvalid_vgalcd_mst_axi4 (wvalid_vgalcd_mst_axi4_data),
  .wready_vgalcd_mst_axi4 (wready_vgalcd_mst_axi4_data),
  .bid_vgalcd_mst_axi4  (bid_vgalcd_mst_axi4_data),
  .bresp_vgalcd_mst_axi4 (bresp_vgalcd_mst_axi4_data),
  .bvalid_vgalcd_mst_axi4 (bvalid_vgalcd_mst_axi4_data),
  .bready_vgalcd_mst_axi4 (bready_vgalcd_mst_axi4_data),
  .arid_vgalcd_mst_axi4 (arid_vgalcd_mst_axi4_data),
  .araddr_vgalcd_mst_axi4 (araddr_vgalcd_mst_axi4_data),
  .arlen_vgalcd_mst_axi4 (arlen_vgalcd_mst_axi4_data),
  .arsize_vgalcd_mst_axi4 (arsize_vgalcd_mst_axi4_data),
  .arburst_vgalcd_mst_axi4 (arburst_vgalcd_mst_axi4_data),
  .arlock_vgalcd_mst_axi4 (arlock_vgalcd_mst_axi4_data),
  .arcache_vgalcd_mst_axi4 (arcache_vgalcd_mst_axi4_data),
  .arprot_vgalcd_mst_axi4 (arprot_vgalcd_mst_axi4_data),
  .arvalid_vgalcd_mst_axi4 (arvalid_vgalcd_mst_axi4_data),
  .arready_vgalcd_mst_axi4 (arready_vgalcd_mst_axi4_data),
  .rid_vgalcd_mst_axi4  (rid_vgalcd_mst_axi4_data),
  .rdata_vgalcd_mst_axi4 (rdata_vgalcd_mst_axi4_data),
  .rresp_vgalcd_mst_axi4 (rresp_vgalcd_mst_axi4_data),
  .rlast_vgalcd_mst_axi4 (rlast_vgalcd_mst_axi4_data),
  .rvalid_vgalcd_mst_axi4 (rvalid_vgalcd_mst_axi4_data),
  .rready_vgalcd_mst_axi4 (rready_vgalcd_mst_axi4_data),
  .paddr_vgalcd_slv_apb4 (paddr_vgalcd_slv_apb4),
  .pselx_vgalcd_slv_apb4 (pselx_vgalcd_slv_apb4),
  .penable_vgalcd_slv_apb4 (penable_vgalcd_slv_apb4),
  .pwrite_vgalcd_slv_apb4 (pwrite_vgalcd_slv_apb4),
  .prdata_vgalcd_slv_apb4 (prdata_vgalcd_slv_apb4),
  .pwdata_vgalcd_slv_apb4 (pwdata_vgalcd_slv_apb4),
  .pprot_vgalcd_slv_apb4 (pprot_vgalcd_slv_apb4),
  .pstrb_vgalcd_slv_apb4 (pstrb_vgalcd_slv_apb4),
  .pready_vgalcd_slv_apb4 (pready_vgalcd_slv_apb4),
  .pslverr_vgalcd_slv_apb4 (pslverr_vgalcd_slv_apb4),
  .clk_peri_100mclk     (clk_peri_100mclk),
  .clk_peri_100mresetn  (clk_peri_100mresetn),
  .paddr_wdg_slv_apb4   (paddr_wdg_slv_apb4),
  .pselx_wdg_slv_apb4   (pselx_wdg_slv_apb4),
  .penable_wdg_slv_apb4 (penable_wdg_slv_apb4),
  .pwrite_wdg_slv_apb4  (pwrite_wdg_slv_apb4),
  .prdata_wdg_slv_apb4  (prdata_wdg_slv_apb4),
  .pwdata_wdg_slv_apb4  (pwdata_wdg_slv_apb4),
  .pprot_wdg_slv_apb4   (pprot_wdg_slv_apb4),
  .pstrb_wdg_slv_apb4   (pstrb_wdg_slv_apb4),
  .pready_wdg_slv_apb4  (pready_wdg_slv_apb4),
  .pslverr_wdg_slv_apb4 (pslverr_wdg_slv_apb4),
  .clk_peri_100mclken   (clk_peri_100mclken)
);


apb4_s_if     uart_slv_apb4 (
  .PADDR                (paddr_uart_slv_apb4),
  .PWDATA               (pwdata_uart_slv_apb4),
  .PWRITE               (pwrite_uart_slv_apb4),
  .PENABLE              (penable_uart_slv_apb4),
  .PSEL                 (pselx_uart_slv_apb4),
  .PRDATA               (prdata_uart_slv_apb4),
  .PSLVERR              (pslverr_uart_slv_apb4),
  .PREADY               (pready_uart_slv_apb4),
  .PPROT                (pprot_uart_slv_apb4),
  .PSTRB                (pstrb_uart_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam uart_slv_apb4.APB_TYPE = 4;
defparam uart_slv_apb4.ID_WIDTH = 4;
defparam uart_slv_apb4.INSTANCE = "uart_slv_apb4";


apb4_s_if     uart_slv_apb4_tpv (
  .PADDR                (paddr_uart_slv_apb4_tpv),
  .PWDATA               (pwdata_uart_slv_apb4_tpv),
  .PWRITE               (pwrite_uart_slv_apb4_tpv),
  .PENABLE              (penable_uart_slv_apb4_tpv),
  .PSEL                 (pselx_uart_slv_apb4_tpv),
  .PRDATA               (prdata_uart_slv_apb4_tpv),
  .PSLVERR              (pslverr_uart_slv_apb4_tpv),
  .PREADY               (pready_uart_slv_apb4_tpv),
  .PPROT                (pprot_uart_slv_apb4_tpv),
  .PSTRB                (pstrb_uart_slv_apb4_tpv),
  .PCLK                 (clk_peri_25mclk),
  .PCLKEN               (clk_peri_25mclken),
  .presetn              (clk_peri_25mresetn)
);
defparam uart_slv_apb4_tpv.APB_TYPE = 4;
defparam uart_slv_apb4_tpv.ID_WIDTH = 4;
defparam uart_slv_apb4_tpv.INSTANCE = "uart_slv_apb4_tpv";


axi4_m_if     vgalcd_mst_axi4 (
  .WAIT_REQ             (wait_req_vgalcd_mst_axi4_event),
  .WAIT_ACK             (wait_ack_vgalcd_mst_axi4_event),
  .WAIT_DATA            (wait_data_vgalcd_mst_axi4_event),
  .EMIT_REQ             (emit_req_vgalcd_mst_axi4_event),
  .EMIT_ACK             (emit_ack_vgalcd_mst_axi4_event),
  .EMIT_DATA            (emit_data_vgalcd_mst_axi4_event),
  .PCLK                 (clk_tb),
  .PRESETn              (resetn_tb),
  .PADDR                (paddr_clk_rst_apb),
  .PWDATA               (pwdata_clk_rst_apb),
  .PWRITE               (pwrite_clk_rst_apb),
  .PENABLE              (penable_clk_rst_apb),
  .PSEL                 (pselx_vgalcd_mst_axi4_apb),
  .PRDATA               (prdata_vgalcd_mst_axi4_apb),
  .PSLVERR              (pslverr_vgalcd_mst_axi4_apb),
  .PREADY               (pready_vgalcd_mst_axi4_apb),
  .ACLK                 (clk_peri_100mclk),
  .ARESETn              (clk_peri_100mresetn),
  .AWID                 (awid_vgalcd_mst_axi4_data),
  .AWADDR               (awaddr_vgalcd_mst_axi4_data),
  .AWLEN                (awlen_vgalcd_mst_axi4_data),
  .AWQOS                (),
  .AWSIZE               (awsize_vgalcd_mst_axi4_data),
  .AWBURST              (awburst_vgalcd_mst_axi4_data),
  .AWLOCK               (awlock_vgalcd_mst_axi4_data),
  .AWCACHE              (awcache_vgalcd_mst_axi4_data),
  .AWPROT               (awprot_vgalcd_mst_axi4_data),
  .AWVALID              (awvalid_vgalcd_mst_axi4_data),
  .AWREGION             (),
  .AWREADY              (awready_vgalcd_mst_axi4_data),
  .WDATA                (wdata_vgalcd_mst_axi4_data),
  .WSTRB                (wstrb_vgalcd_mst_axi4_data),
  .WLAST                (wlast_vgalcd_mst_axi4_data),
  .WVALID               (wvalid_vgalcd_mst_axi4_data),
  .WREADY               (wready_vgalcd_mst_axi4_data),
  .BID                  (bid_vgalcd_mst_axi4_data),
  .BRESP                (bresp_vgalcd_mst_axi4_data),
  .BVALID               (bvalid_vgalcd_mst_axi4_data),
  .BREADY               (bready_vgalcd_mst_axi4_data),
  .ARID                 (arid_vgalcd_mst_axi4_data),
  .ARADDR               (araddr_vgalcd_mst_axi4_data),
  .ARLEN                (arlen_vgalcd_mst_axi4_data),
  .ARQOS                (),
  .ARSIZE               (arsize_vgalcd_mst_axi4_data),
  .ARBURST              (arburst_vgalcd_mst_axi4_data),
  .ARLOCK               (arlock_vgalcd_mst_axi4_data),
  .ARCACHE              (arcache_vgalcd_mst_axi4_data),
  .ARPROT               (arprot_vgalcd_mst_axi4_data),
  .ARVALID              (arvalid_vgalcd_mst_axi4_data),
  .ARREGION             (),
  .ARREADY              (arready_vgalcd_mst_axi4_data),
  .RID                  (rid_vgalcd_mst_axi4_data),
  .RDATA                (rdata_vgalcd_mst_axi4_data),
  .RRESP                (rresp_vgalcd_mst_axi4_data),
  .RLAST                (rlast_vgalcd_mst_axi4_data),
  .RVALID               (rvalid_vgalcd_mst_axi4_data),
  .RREADY               (rready_vgalcd_mst_axi4_data),
  .AWUSER               (),
  .WUSER                (),
  .BUSER                ({(vgalcd_mst_axi4_BUSER_WIDTH-1 + 1){1'b0}}),
  .ARUSER               (),
  .RUSER                ({(vgalcd_mst_axi4_RUSER_WIDTH-1 + 1){1'b0}}),
  .ACLKEN               (1'b0)
);
defparam vgalcd_mst_axi4.ADDR_WIDTH = 32;
defparam vgalcd_mst_axi4.ARUSER_WIDTH = vgalcd_mst_axi4_ARUSER_WIDTH;
defparam vgalcd_mst_axi4.AWUSER_WIDTH = vgalcd_mst_axi4_AWUSER_WIDTH;
defparam vgalcd_mst_axi4.BUSER_WIDTH = vgalcd_mst_axi4_BUSER_WIDTH;
defparam vgalcd_mst_axi4.DATA_WIDTH = 64;
defparam vgalcd_mst_axi4.DriveOnlyOnEnable = vgalcd_mst_axi4_DriveOnlyOnEnable;
defparam vgalcd_mst_axi4.EW_WIDTH = 16;
defparam vgalcd_mst_axi4.ID_WIDTH = 3;
defparam vgalcd_mst_axi4.INSTANCE = "vgalcd_mst_axi4";
defparam vgalcd_mst_axi4.MaxWaits = vgalcd_mst_axi4_MaxWaits;
defparam vgalcd_mst_axi4.PortIsInternal = vgalcd_mst_axi4_PortIsInternal;
defparam vgalcd_mst_axi4.RUSER_WIDTH = vgalcd_mst_axi4_RUSER_WIDTH;
defparam vgalcd_mst_axi4.RecMaxWaitOn = vgalcd_mst_axi4_RecMaxWaitOn;
defparam vgalcd_mst_axi4.RecommendOn = vgalcd_mst_axi4_RecommendOn;
defparam vgalcd_mst_axi4.STRB_WIDTH = 8;
defparam vgalcd_mst_axi4.USE_X = vgalcd_mst_axi4_USE_X;
defparam vgalcd_mst_axi4.VALID_WIDTH = 1;
defparam vgalcd_mst_axi4.WUSER_WIDTH = vgalcd_mst_axi4_WUSER_WIDTH;
defparam vgalcd_mst_axi4.leading_write_depth = vgalcd_mst_axi4_leading_write_depth;
defparam vgalcd_mst_axi4.limit_issuing_capability = 0;
defparam vgalcd_mst_axi4.read_acceptance_capability = vgalcd_mst_axi4_read_acceptance_capability;
defparam vgalcd_mst_axi4.unlimited_acceptance_capability = 0;
defparam vgalcd_mst_axi4.write_acceptance_capability = vgalcd_mst_axi4_write_acceptance_capability;


apb4_s_if     vgalcd_slv_apb4 (
  .PADDR                (paddr_vgalcd_slv_apb4),
  .PWDATA               (pwdata_vgalcd_slv_apb4),
  .PWRITE               (pwrite_vgalcd_slv_apb4),
  .PENABLE              (penable_vgalcd_slv_apb4),
  .PSEL                 (pselx_vgalcd_slv_apb4),
  .PRDATA               (prdata_vgalcd_slv_apb4),
  .PSLVERR              (pslverr_vgalcd_slv_apb4),
  .PREADY               (pready_vgalcd_slv_apb4),
  .PPROT                (pprot_vgalcd_slv_apb4),
  .PSTRB                (pstrb_vgalcd_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam vgalcd_slv_apb4.APB_TYPE = 4;
defparam vgalcd_slv_apb4.ID_WIDTH = 4;
defparam vgalcd_slv_apb4.INSTANCE = "vgalcd_slv_apb4";


apb4_s_if     wdg_slv_apb4 (
  .PADDR                (paddr_wdg_slv_apb4),
  .PWDATA               (pwdata_wdg_slv_apb4),
  .PWRITE               (pwrite_wdg_slv_apb4),
  .PENABLE              (penable_wdg_slv_apb4),
  .PSEL                 (pselx_wdg_slv_apb4),
  .PRDATA               (prdata_wdg_slv_apb4),
  .PSLVERR              (pslverr_wdg_slv_apb4),
  .PREADY               (pready_wdg_slv_apb4),
  .PPROT                (pprot_wdg_slv_apb4),
  .PSTRB                (pstrb_wdg_slv_apb4),
  .PCLK                 (clk_peri_100mclk),
  .PCLKEN               (clk_peri_100mclken),
  .presetn              (clk_peri_100mresetn)
);
defparam wdg_slv_apb4.APB_TYPE = 4;
defparam wdg_slv_apb4.ID_WIDTH = 4;
defparam wdg_slv_apb4.INSTANCE = "wdg_slv_apb4";



endmodule
